Abstract: A broadband measurement system and a measurement method for broadband property are provided. The signal measurement apparatus is used to transmit a measuring signal belonging to a first frequency domain from its measuring port. Two ports of the signal converter are used to connect with two measuring ports of the signal measurement apparatus. The first passive mixer of the signal converter is configured as bidirectional, and the second passive mixer of the signal converter is configured as bidirectional. Two mixers are used to convert the signals from the first frequency domain into a second frequency domain, and convert the signals from the second frequency domain into the first frequency domain.

Abstract: A rough road escaping system for a vehicle having an electric-axle and a method thereof, may enable wheels respectively connected to first and second axle shafts to easily escape from a rough road by generating a recoiling force of the vehicle through motor torque control that alternately applies several time forward driving torque output from a first motor included in a rear wheel-first electric-axle to a first axle shaft and backward driving torque output from a second motor included in a rear wheel-second electronic-axle to a second axle shaft.

Abstract: The present disclosure provides methods and a non-transitory computer readable media for resistance and capacitance (RC) extraction. The method comprises: receiving an electronic layout; selecting a two-dimensional (2D) conductive element from the electronic layout, wherein an aspect ratio of the 2D conductive element is lower than a predetermined threshold; partitioning the 2D conductive element into a plurality of polygons; determining a parasitic capacitance value for each polygon; determining multiple parasitic resistance values for each polygon; determining a total capacitance value of the 2D conductive element based on the parasitic capacitance value for each polygon; and determining a total resistance value of the 2D conductive element based on the multiple parasitic resistance values for each polygon.

Abstract: A method for creating a modified flight simulation program for a flight simulation system includes: obtaining a demonstration flight record associated with a preset track route of a virtual airplane; generating an add-on content pack for the flight simulation program based on the demonstration flight record; and merging the add-on content pack to the flight simulation program to create a modified flight simulation program. The generation of the add-on content pack includes: mapping the preset track route to geographical coordinate data in the real world, creating a first program module associated with a demonstration mode enabling a demonstration virtual flight along the preset track route, creating a second program module associated with an assisted flight mode enabling user control for a virtual flight within a free-flight space, and creating the add-on content pack that includes the first and the second program modules.

Abstract: Embodiments of the present disclosure generally relate to electroluminescent devices, such as organic light-emitting diodes, and displays including electroluminescent devices. In an embodiment is provided an electroluminescent device that includes a pixel defining layer, an organic emitting unit disposed over at least a portion of the pixel defining layer, and a filler layer disposed over at least a portion of the organic emitting unit, wherein a refractive index of the pixel defining layer is lower than a refractive index of the filler layer, and wherein the refractive index of the pixel defining layer is lower than a refractive index of one or more layers of the organic emitting unit. In another embodiment is provided a display device that includes a substrate, a thin film transistor formed on the substrate, an interconnection electrically coupled to the thin film transistor, and an electroluminescent device electrically coupled to the interconnection.

Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Abstract: An additive, liquid-crystal composition and a liquid-crystal display using the additive are provided. The additive includes a first additive molecule having a structure represented by formula (I): wherein Ri1, Ri2, Ri3, Ai1, Ai2, Zi, m1 and m2 are defined as in the specification.

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

Abstract: A method of forming a semiconductor device including: providing a first circuit cell including a first pin cell; forming a connecting path originated from the first pin cell of the first circuit cell; performing an Electromigration (EM) checking process with a first parasitic capacitance of the first pin cell and a second parasitic capacitance of the connecting path by loading a loading capacitance file to determine whether the loading capacitance of the first pin cell is larger than a first predetermined capacitance; and substituting a second pin cell for the first pin cell when the loading capacitance of the first pin cell is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell.

Abstract: An organic light-emitting diode (OLED) device includes a substrate, a well structure on the substrate with the well structure having a recess with side walls and a floor, a lower metal layer covering the floor and side-walls of the well, an upper conductive layer on the lower metal layer covering the floor of the well and contacting the lower metal layer, the upper conductive layer having outer edges at about an intersection of the side walls and the floor, a dielectric layer formed of an oxide of the lower metal layer covering the side walls of the well without covering the upper conductive layer, a stack of OLED layers covering at least the floor of the well, the upper conductive layer providing an electrode for the stack of OLED layers, and a light extraction layer (LEL) in the well over the stack of OLED layers and the dielectric layer.

Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.

Abstract: An organic light-emitting diode (OLED) device includes a substrate, a well structure on the substrate with the well structure having a recess with side walls and a floor, a lower metal layer covering the floor and side-walls of the well, an upper conductive layer on the lower metal layer covering the floor of the well and contacting the lower metal layer, the upper conductive layer having outer edges at about an intersection of the side walls and the floor, a dielectric layer formed of an oxide of the lower metal layer covering the side walls of the well without covering the upper conductive layer, a stack of OLED layers covering at least the floor of the well, the upper conductive layer providing an electrode for the stack of OLED layers, and a light extraction layer (LEL) in the well over the stack of OLED layers and the dielectric layer.

Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.

Abstract: A light-emitting pixel structure is described that may include a group of light-emitting diode structures, where each of the light-emitting diode structures is operable to emit light characterized by a different peak emission wavelength. The structures may also include a patterned light absorption barrier characterized by a group of openings in the barrier, where each of the openings permit a transmission of a portion of the light from one of the light-emitting diode structures through the barrier. The structures may further include a metasurface layer operable to change a direction of at least some of the light transmitted through the openings of the patterned light absorption barrier from the light-emitting diode structures.