Patents by Inventor Wan-don Kim
Wan-don Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136416Abstract: A semiconductor device includes an active pattern extending in a first direction, a plurality of gate structures on the active pattern spaced in the first direction, and including a gate electrode extending in a second direction, a source/drain pattern between adjacent gate structures, a silicide mask pattern on the source/drain pattern, an upper surface of the silicide mask pattern being lower than an upper surface of the gate electrode, a source/drain contact on the source/drain pattern connected to the source/drain pattern, and a contact silicide film between the source/drain contact and the source/drain pattern in contact with a bottom surface of the silicide mask pattern, wherein a height from a lowermost part of the source/drain pattern to a lowermost part of the source/drain contact is smaller than a height from the lowermost part of the source/drain pattern to the bottom surface of the silicide mask pattern.Type: ApplicationFiled: August 15, 2023Publication date: April 25, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jun Ki Park, Sung Hwan Kim, Wan Don Kim, Heung Seok Ryu
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Patent number: 11967630Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.Type: GrantFiled: February 11, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung Hoon Lee, Wan Don Kim, Jong Ho Park, Sang Jin Hyun
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Publication number: 20240120279Abstract: A semiconductor device may include a first film and a second film defining parts of a trench, a plug conductive film, a via, and a wiring in the trench. The trench may include a second sub-trench having a second width below a first sub-trench having a first width. The plug conductive film may extend from a first side of the first film to penetrate a bottom face of the trench. An uppermost face of the plug conducive film may be in the trench. The via may include an insulating liner between the plug conductive film and the first film. The uppermost face of the plug conductive film and at least a part of a side wall of the plug conductive film may be in contact with the wiring. An upper face of the insulating liner may be exposed by a bottom face of the second sub-trench.Type: ApplicationFiled: September 21, 2023Publication date: April 11, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong Hyuk YIM, Wan Don KIM, Hyun Bae LEE, Hyo Seok CHOI, Geun Woo KIM
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Patent number: 11949012Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: GrantFiled: December 8, 2020Date of Patent: April 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
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Publication number: 20240063276Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: ApplicationFiled: October 17, 2023Publication date: February 22, 2024Inventors: Heon Bok LEE, Dae Yong KIM, Wan Don KIM, Jeong Hyuk YIM, Won Keun CHUNG, Hyo Seok CHOI, Sang Jin HYUN
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Patent number: 11854979Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.Type: GrantFiled: July 19, 2021Date of Patent: December 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jang Eun Lee, Min Joo Lee, Wan Don Kim, Hyeon Jin Shin, Hyun Bae Lee, Hyun Seok Lim
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Patent number: 11799004Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: GrantFiled: March 15, 2022Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heon Bok Lee, Dae Yong Kim, Wan Don Kim, Jeong Hyuk Yim, Won Keun Chung, Hyo Seok Choi, Sang Jin Hyun
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Publication number: 20230026976Abstract: A semiconductor device includes: a substrate; a first interlayer insulating layer on the substrate; a first wiring pattern in a first trench of the first interlayer insulating layer; a second interlayer insulating layer on the first interlayer insulating layer; a second wiring pattern in a second trench of the second interlayer insulating layer; a third interlayer insulating layer on the second interlayer insulating layer; a third wiring pattern in a third trench of the third interlayer insulating layer, and including a wiring barrier layer and a wiring filling layer, wherein the wiring filling layer contacts the third interlayer insulating layer; a via trench extending from the first wiring pattern to the third trench; and a via including a via barrier layer and a via filling layer. The via barrier layer is in the via trench. The via filling layer contacts the first wiring pattern and the wiring filling layer.Type: ApplicationFiled: February 4, 2022Publication date: January 26, 2023Inventors: Sun Young Noh, Eui Bok Lee, Wan Don Kim, Han Min Jang
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Publication number: 20220208679Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.Type: ApplicationFiled: September 14, 2021Publication date: June 30, 2022Inventors: Eui Bok Lee, Wan Don Kim, Hyun Bae Lee, Yoon Tae Hwang
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Publication number: 20220199790Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: ApplicationFiled: March 15, 2022Publication date: June 23, 2022Inventors: Heon Bok LEE, Dae Yong KIM, Wan Don Kim, Jeong Hyuk YIM, Won Keun CHUNG, Hyo Seok CHOI, Sang Jin HYUN
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Publication number: 20220165861Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.Type: ApplicationFiled: February 11, 2022Publication date: May 26, 2022Inventors: Byoung Hoon LEE, Wan Don KIM, Jong Ho PARK, Sang Jin HYUN
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Patent number: 11296196Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: GrantFiled: November 26, 2019Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heon Bok Lee, Dae Yong Kim, Wan Don Kim, Jeong Hyuk Yim, Won Keun Chung, Hyo Seok Choi, Sang Jin Hyun
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Patent number: 11282939Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.Type: GrantFiled: February 7, 2019Date of Patent: March 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung Hoon Lee, Wan Don Kim, Jong Ho Park, Sang Jin Hyun
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Publication number: 20220084952Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.Type: ApplicationFiled: July 19, 2021Publication date: March 17, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jang Eun LEE, Min Joo LEE, Wan Don KIM, Hyeon Jin SHIN, Hyun Bae LEE, Hyun Seok LIM
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Publication number: 20220059533Abstract: A semiconductor device includes first and second active patterns disposed on a substrate, a field insulating film disposed between the first and second active patterns, a first gate structure intersecting the first active pattern, and a second gate structure intersecting the second active pattern, in which the first gate structure includes a first gate insulating film on the first active pattern, a first upper insertion film on the first gate insulating film, and a first upper conductive film on the first upper insertion film, and the second gate structure includes a second gate insulating film on the second active pattern, a second upper insertion film on the second gate insulating film, and a second upper conductive film on the second upper insertion film. Each of the first and second upper insertion films may include an aluminum nitride film. Each of the first and second upper conductive films may include aluminum.Type: ApplicationFiled: March 31, 2021Publication date: February 24, 2022Inventors: SU YOUNG BAE, Jong Ho Park, Dong Soo Lee, Wan Don Kim
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Publication number: 20220013467Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.Type: ApplicationFiled: June 25, 2021Publication date: January 13, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jang Eun LEE, Min Joo LEE, Wan Don KIM, Hyun Bae LEE
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Publication number: 20210119058Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: ApplicationFiled: December 8, 2020Publication date: April 22, 2021Inventors: Jong Ho PARK, Wan Don KIM, Weon Hong KIM, Hyeon Jun BAEK, Byoung Hoon LEE, Jeong Hyuk YIM, Sang Jin HYUN
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Patent number: 10879392Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: GrantFiled: June 25, 2019Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
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Patent number: 10770560Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.Type: GrantFiled: December 10, 2018Date of Patent: September 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong Hyuk Yim, Kug Hwan Kim, Wan Don Kim, Jung Min Park, Jong Ho Park, Byoung Hoon Lee, Yong Ho Ha, Sang Jin Hyun, Hye Ri Hong
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Patent number: 10734280Abstract: An integrated circuit (IC) device includes a substrate having a fin-type active region extending in a first direction, a gate structure intersecting the fin-type active region on the substrate, the gate structure extending in a second direction perpendicular to the first direction and parallel to a top surface of the substrate, source and drain regions on both sides of the gate structure, and a first contact structure electrically connected to one of the source and drain regions, the first contact structure including a first contact plug including a first material and a first wetting layer surrounding the first contact plug, the first wetting layer including a second material having a lattice constant that differs from a lattice constant of the first material by about 10% or less.Type: GrantFiled: October 9, 2018Date of Patent: August 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-hyuk Yim, Kuo Tai Huang, Wan-don Kim, Sang-jin Hyun