Abstract: A pixel circuit includes first, second, and third transistors, and first and second capacitors, wherein the first transistor is controlled by a scan line and is configured to controllably couple a data line to the first capacitor and a gate electrode of the second transistor, the second transistor is controlled by a voltage provided by the first and second capacitors, the third transistor is controlled by the scan line and is configured to controllably couple a first power supply to the second capacitor, and the first power supply is controllably coupled to a light source by the second transistor.

Abstract: A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.