Abstract: An assembled cabinet and power connection boards thereof, in which side board assemblies of the assembled cabinet are stacked in a way that upper power connectors of a power connection board of a lower side board assembly among two adjacent stacked up side board assemblies are electrically connected with lower power connectors of a power connection board of the an upper side board assembly among the two adjacent stacked up side board assemblies, so as to preserve the versatility and flexibility of the installation of the assembled cabinet while allowing stable power supply to the electronic locks of the assembled cabinet.

Abstract: An integrated circuit (IC) device includes memory cells each including first through fourth memory elements. The first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. The second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. The first and second memory elements are arranged in a first row along the first axis. The third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. The fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. The third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.

Abstract: The present disclosure provides a motor drive integrated on-board charger to reduce the quantity of components in an electric system of an electric vehicle. Reduction of components is achieved by utilizing the motor and the motor driving inverter as a part of the on-board charger in the charging mode. By controlling relays, electrical connections of the system may be reconfigured according to its mode of operation. In one aspect, the motor and the motor driving inverter play the roles of a boost PFC, a current regulator, or both.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

Abstract: Techniques are described herein that are capable of automatic mapping of a question or compliance controls associated with a compliance standard to compliance controls associated with another compliance standard. Reference controls having respective first subsets of text-based features are identified. A question having a second subset of the text-based features or custom controls having respective second subsets of the text-based features are identified. Scores for the respective reference controls are determined for the question or each custom control using a supervised natural language processing machine learning model based at least on the first subsets of the text-based features and the second subset(s) of the text-based features. A compliance map is generated by automatically mapping the question or each custom control to a respective subset of the reference controls using the supervised natural language processing machine learning model based at least on the scores.

Abstract: Provided is a system for detecting an anomaly in a multivariate time series that includes at least one processor programmed or configured to receive a dataset of a plurality of data instances, wherein each data instance comprises a time series of data points, determine a set of target data instances based on the dataset, determine a set of historical data instances based on the dataset, generate, based on the set of target data instances, a true value matrix, a true frequency matrix, and a true correlation matrix, generate a forecast value matrix, a forecast frequency matrix, and a forecast correlation matrix based on the set of target data instances and the set of historical data instances, determine an amount of forecasting error, and determine whether the amount of forecasting error corresponds to an anomalous event associated with the dataset of data instances. Methods and computer program products are also provided.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A computing system performs artificial-intelligence (AI) super-resolution (SR). The computing system includes multiple processors, which further includes a graphics processing unit (GPU) and an AI processing unit (APU). The computing system also includes a memory to store AI models. When detecting an indication that the loading of the GPU exceeds a threshold, the processors reduce the resolution of a video output from the GPU in response to the indication. One of the AI models is selected based on graphics scenes in the video and the respective power consumption estimates of the AI models. The processors then perform AI SR operations on the video using the selected AI model to restore the resolution of the video for display.

Abstract: The present disclosure generally relates to underwater user interfaces.

Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.

Abstract: A method includes receiving a first data set comprising embeddings of first and second types, generating a fixed adjacency matrix from the first dataset, and applying a first stochastic binary mask to the fixed adjacency matrix to obtain a first subgraph of the fixed adjacency matrix. The method also includes processing the first subgraph through a first layer of a graph convolutional network (GCN) to obtain a first embedding matrix, and applying a second stochastic binary mask to the fixed adjacency matrix to obtain a second subgraph of the fixed adjacency matrix. The method includes processing the first embedding matrix and the second subgraph through a second layer of the GCN to obtain a second embedding matrix, and then determining a plurality of gradients of a loss function, and modifying the first stochastic binary mask and the second stochastic binary mask using at least one of the plurality of gradients.

Abstract: A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.

Abstract: There is provided peptidic compounds of Formula I, A or B(Rradn6-[linker]-RL-Xaa1-Xaa2-Xaa3-Xaa4-Xaa5-Xaa6-Xaa7-Xaa8-?-Xaa9-NH2). Xaa1 is D-Phe, Cpa, D-Cpa, Nal, D-Nal, 2-Nal, or D-2-Nal; Xaa2 is Asn, Gln, Hse, Cit or His. Xaa3 is Trp, Bta, Trp(Me), Trp(7-Me), Trp(6-Me), Trp(5-Me), Trp(4-Me), Trp(2-Me), Trp(7-F), Trp(6-F), Trp(5-F), Trp(4-F), Trp(5-OH), or ?Me-Trp. Xaa4 is Ala or Ser. Xaa5 is Val, Cpg, or Tle. Xaa6 is Gly, NMe-Gly, or D-Ala. Xaa7 is His or NMe-His. Xaa8 is Leu or Phe. Xaa9-NH2 is a C-terminally amidated amino acid residue selected from Pro, 4-oxa-L-Pro, Me2 Thz, or Thz. ? represents a peptide bond or reduced peptide bond joining Xaa8 to Xaa9. Rradn6 is 1-5 radiolabeling groups. There is also provided the use of such compounds as imaging agents or therapeutic agents.

Abstract: A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: An electronic lock for an assembled cabinet, including a lock shell, a locking and unlocking assembly mounted on the lock shell, an electronic driving device, a wireless communication device, a control circuit board, and a power supply. The control circuit board is electrically connected to the electronic driving device, the wireless communication device, and the power supply. The electronic driving device transmits motion to the locking and unlocking assembly. The electronic lock is adaptable to free combination of an assembled cabinet to provide easy installation and convenient use.

Abstract: Methods of treating cancers using a BCMAxCD3 bispecific antibody are described.