Abstract: The present disclosure generally relates to underwater user interfaces.

Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.

Abstract: A method includes receiving a first data set comprising embeddings of first and second types, generating a fixed adjacency matrix from the first dataset, and applying a first stochastic binary mask to the fixed adjacency matrix to obtain a first subgraph of the fixed adjacency matrix. The method also includes processing the first subgraph through a first layer of a graph convolutional network (GCN) to obtain a first embedding matrix, and applying a second stochastic binary mask to the fixed adjacency matrix to obtain a second subgraph of the fixed adjacency matrix. The method includes processing the first embedding matrix and the second subgraph through a second layer of the GCN to obtain a second embedding matrix, and then determining a plurality of gradients of a loss function, and modifying the first stochastic binary mask and the second stochastic binary mask using at least one of the plurality of gradients.

Abstract: A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.

Abstract: There is provided peptidic compounds of Formula I, A or B(Rradn6-[linker]-RL-Xaa1-Xaa2-Xaa3-Xaa4-Xaa5-Xaa6-Xaa7-Xaa8-?-Xaa9-NH2). Xaa1 is D-Phe, Cpa, D-Cpa, Nal, D-Nal, 2-Nal, or D-2-Nal; Xaa2 is Asn, Gln, Hse, Cit or His. Xaa3 is Trp, Bta, Trp(Me), Trp(7-Me), Trp(6-Me), Trp(5-Me), Trp(4-Me), Trp(2-Me), Trp(7-F), Trp(6-F), Trp(5-F), Trp(4-F), Trp(5-OH), or ?Me-Trp. Xaa4 is Ala or Ser. Xaa5 is Val, Cpg, or Tle. Xaa6 is Gly, NMe-Gly, or D-Ala. Xaa7 is His or NMe-His. Xaa8 is Leu or Phe. Xaa9-NH2 is a C-terminally amidated amino acid residue selected from Pro, 4-oxa-L-Pro, Me2 Thz, or Thz. ? represents a peptide bond or reduced peptide bond joining Xaa8 to Xaa9. Rradn6 is 1-5 radiolabeling groups. There is also provided the use of such compounds as imaging agents or therapeutic agents.

Abstract: A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: An electronic lock for an assembled cabinet, including a lock shell, a locking and unlocking assembly mounted on the lock shell, an electronic driving device, a wireless communication device, a control circuit board, and a power supply. The control circuit board is electrically connected to the electronic driving device, the wireless communication device, and the power supply. The electronic driving device transmits motion to the locking and unlocking assembly. The electronic lock is adaptable to free combination of an assembled cabinet to provide easy installation and convenient use.

Abstract: Methods of treating cancers using a BCMAxCD3 bispecific antibody are described.

Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.

Abstract: Disclosed herein are heterocyclic compounds, for example, according to the following formula and analogs thereof: that inhibit the activity of FLT3. Also described are specific covalent inhibitors of FLT3. Also disclosed are pharmaceutical compositions that include the compounds. Methods of using the FLT3 inhibitors are disclosed, alone or in combination with other therapeutic agents, for the treatment of proliferative diseases or conditions, including hematological malignancies and other diseases or conditions dependent on FLT3 activity.

Abstract: A User Equipment (UE) including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from one or more peer UEs. The controller determines a Sidelink (SL) Discontinuous Reception (DRX) configuration set, and applies the SL DRX configuration set to enable a DRX operation for SL communications with the peer UEs via the wireless transceiver; wherein the SL DRX configuration set is determined based on one of the following: one or more types of one or more SL services which the UE is participating with the peer UEs; one or more SL DRX configurations received from the peer UEs; and control information received from a Base Station (BS).

Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.

Abstract: A method comprises forming a gate dielectric cap over a gate structure; forming source/drain contacts over the semiconductor substrate, with the gate dielectric cap laterally between the source/drain contacts; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the etch-resistant layer and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the via opening such that one of the source/drain contacts is exposed, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening.

Abstract: Disclosed herein are an adhesion blocking element, a three-dimensional printing device and a three-dimensional printing method. The adhesion blocking element comprises: one light-transmittable main body comprising a first surface and a second surface which are disposed opposite to each other, and side faces connecting the first surface and the second surface; and a plurality of microstructures arranged on the main body, wherein each microstructure has one cavity formed in the main body and one first open face which is arranged on the first surface of the main body and communicated to the cavity. The present invention decreases the adhesion between the adhesion blocking element and the cured layer by improving the structure of the adhesion blocking element itself, and eliminates the negative pressure adsorption between the cured layer and the adhesion blocking element, so that it is easier to peel the adhesion blocking element off from the cured layer.

Abstract: Compositions and methods for early diagnosis, risk stratification, and effective management and treatment of patients with hepatocellular carcinoma are provided. The compositions and methods selectively target S100A10, for effective detection of S100A10 in a subject, for example, from plasma samples or from tissue biopsy, and for effective inhibiting and/or reducing the activities and/or quantities of S100A10 in vitro and/or in vivo. Methods for selecting patients who would be amenable for the disclosed therapies and for treating such patients are also described.

Abstract: A high-throughput automated preprocessing method and a system are applied to a nucleic acid preprocessing apparatus including a control system, a sample transfer area, a nucleic acid extraction area, and a reagent setup area. The control system includes a user interface and guides a user to set up on the user interface. In the sample transfer area, the method includes steps of: a user selecting a sampling tube type, a test protocol and an extraction protocol on the user interface, and the control system performing a sample transfer task. In the nucleic acid extraction area, the method includes steps of: the control system performing a nucleic acid extraction task based on the selected extraction protocol. In the reagent setup area, the method includes steps of: the control system performing a reagent deployment task based on the selected test protocol, and the control system performing a nucleic acid transfer task.

Abstract: A terminal structure includes an electrically conductive post, an electrically conductive flange, and a stress buffer. The electrically conductive post has a bottom surface at a first level and an upper sidewall laterally covered by the stress buffer. The stress buffer has a bottom surface at a second level between the top surface and the bottom surface of the electrically conductive post. The electrically conductive flange extends laterally from the upper sidewall of the electrically conductive post to an outer peripheral edge thereof, and has a depression surface at a third level between the top surface and the bottom surface of the electrically conductive post. Accordingly, the terminal structure has multi-level staggered configuration and is advantageous to achieving the desired wetting height for robust visual inspection and improving primary and secondary board-level reliability.

Abstract: A method (of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second S/D terminal; and wherein the first source/drain voltage is lower than the gate voltage.

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.