Abstract: A method and apparatus for timing acquisition of partial response class IV Signaling is described. The invention uses an acquisition logic block to determine an output sequence that best matches a preamble pattern. The logic block analyzes current quantizer output X and the two previous decisions X.sub.n and X.sub.n-1. The logic uses these values to determine the next value X.sub.n+1 so that the best match occurs. The invention is implemented with OR gates, AND gates, and D flip-flops and can operate in acquiring mode or tracking mode.

Abstract: The present invention describes an improved RLL channel utilizing a closed-loop clock recovery scheme and a simplified decoding algorithm. (1,7) run-length-limited (RLL) code is used to reduce the magnetic nonlinearity problem posed by prior art PRML systems. In the preferred embodiment of the present invention, the analog data signal amplified, filtered and equalized to approximate an ideal waveform. The signal is then sampled and decoded into binary data. The clock recovery circuit is designed to sample the analog data such that the signal peak lies centered between consecutive sample points. It is thus made possible for the phase error to be extracted from a direct comparison of neighboring sample values. The phase error is then used to adjust the clock signal for the following samples. In the decoding algorithm of the present invention, by making useful approximations, the complexity of the decision functions is reduced, along with the number of required look-ahead samples.