Patents by Inventor Wang Zheng

Wang Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140367803
    Abstract: An intermediate semiconductor structure of a FinFET device in fabrication includes a substrate, a plurality of fin structures coupled to the substrate and a dummy gate disposed perpendicularly over the fin structures. A portion of the dummy gate is removed between the fin structures to create one or more vias and the one or more vias are filled with a dielectric. The dummy gate is then replaced with a metal gate formed around the dielectric-filled vias.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Inventors: Hong YU, Wang ZHENG, Huang LIU, Yongsik MOON
  • Patent number: 8286151
    Abstract: The present invention provides an overlay instruction accessing unit and method, and a method and apparatus for compressing and storing a program.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: October 9, 2012
    Assignee: International Business Machines Corporation
    Inventors: Liang Chen, Kuan Feng, Wang Zheng, Min Zhu
  • Publication number: 20090089507
    Abstract: The present invention provides an overlay instruction accessing unit and method, and a method and apparatus for compressing and storing a program.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Applicant: International Business Machines Corporation
    Inventors: Liang Chen, Kuan Feng, Wang Zheng, Min Zhu
  • Patent number: 7022583
    Abstract: A method of forming a shallow trench isolation device in order to prevent kick effects comprising a semiconductor structure having a patterned masking layer formed thereon. A shallow trench is formed in the semiconductor structure by using the patterned masking layer as a mask. A liner oxide layer and a doped dielectric layer are formed in sequence on the semiconductor structure to cover the surface of the shallow trench. A layer of oxide is formed on the semiconductor structure to fill the shallow trench. The dopants in the doped dielectric layer diffuse into the semiconductor structure surrounding the shallow trench to form an ion doped area, thereby increasing the threshold voltage caused by the recess on the corner structure in order to prevent the kick effect.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: April 4, 2006
    Assignee: Grace Semiconductor Manufacturing Corporation
    Inventors: DeXue Leng, Wang Zheng
  • Publication number: 20030236399
    Abstract: The present invention is a method of improving the quality of taste of a sweetener such as stevioside comprising the steps of (a) providing a predetermined aqueous solution of Stevioside; (b) adding a predetermined substrate with a predetermined dextrose equivalent (D.E.) (c) mixing the aqueous solution of stevioside and substrate; (d) adding a predetermined transferase in a predetermined quantity to form a reacting solution; and (e) allowing the reacting solution to react for a predetermined reaction time under a predetermined controlled temperature to form a resulting product. Taking consideration of the production cost and percentage yield of the product, a predetermined set of reaction conditions are selected such that the percentage yield of 60-86% is achieved and the qualities of the taste of the sweentener such as the quality of sweetness, the pleasantness, the after-taste, the similarity to sucrose are improved.
    Type: Application
    Filed: June 23, 2003
    Publication date: December 25, 2003
    Applicant: Shangdong Hua Xian Stevia Co., Ltd.
    Inventors: Shu Wang Zheng, Guang San Che, Shao Lang Zhou, Qiang Huo