Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.

Abstract: Provided is a novel anti-armyworm use of cry1Ab/cry1AcZM gene. Said gene can be used for controlling or killing Mythimna separate (Walker) and reducing injury to plants by Mythimna separate.

Abstract: An insect-resistant herbicide-tolerant corn transformation event, and a related creation method, a detection method, and application thereof are provided herein. Using the corn inbred line Xiang 249 as a receptor, by means of agrobacterium-mediated genetic transformation, obtaining a corn plant with an exogenous gene insert inserted at a specific genomic locus, the exogenous gene insert comprising the following three genes: an insect-resistant gene, a glufosinate resistant gene, and a glyphosate resistant gene. In the obtained transformation event, the inserted exogenous genes are positioned at a non-functional locus of the corn genome, and do not affect the expression of the other genes of the receptor plant, such that the transgenic corn plant maintains good agronomic traits whilst acquiring insect resistance and herbicide tolerance.

Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.

Abstract: Production of transformed plants is achieved by placing Agrobacterium-inoculated explants directly onto a medium containing selective agents for suppressing growth of Agrobacterium and killing non-transformed explant cells.

Abstract: An insect-resistant herbicide-tolerant corn transformation event, and a related creation method, a detection method, and application thereof are provided herein. Using the corn inbred line Xiang 249 as a receptor, by means of agrobacterium-mediated genetic transformation, obtaining a corn plant with an exogenous gene insert inserted at a specific genomic locus, the exogenous gene insert comprising the following three genes: an insect-resistant gene, a glufosinate resistant gene, and a glyphosate resistant gene. In the obtained transformation event, the inserted exogenous genes are positioned at a non-functional locus of the corn genome, and do not affect the expression of the other genes of the receptor plant, such that the transgenic corn plant maintains good agronomic traits whilst acquiring insect resistance and herbicide tolerance.

Abstract: Provided is a novel anti-armyworm use of cry1Ab/cry1AcZM gene. Said gene can be used for controlling or killing Mythimna separate (Walker) and reducing injury to plants by Mythimna separate.

Abstract: The present disclosure relates to a gene sequence Cry1Ab/Cry1AcZM, an expression cassette containing the gene, an expression vector, a host cell and the use thereof in plant breeding. The protein encoded by an insect-resistant gene according to the disclosure can be expressed in a monocotyledonous plant and further used for culturing an insect-resistant transgenic monocotyledonous plant harboring transgenes Cry1Ab/Cry1AcZM. Bioassay tests prove that the modified and synthesized gene sequence Cry1Ab/Cry1AcZM and the expression product of the constructed vector according to the disclosure have a killing effect on lepidopteran pests.

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.

Abstract: The present disclosure relates to a gene sequence Cry1Ab/Cry1AcZM, an expression cassette containing the gene, an expression vector, a host cell and the use thereof in plant breeding. The protein encoded by an insect-resistant gene according to the disclosure can be expressed in a monocotyledonous plant and further used for culturing an insect-resistant transgenic monocotyledonous plant harboring transgenes Cry1Ab/Cry1AcZM. Bioassay tests prove that the modified and synthesized gene sequence Cry1Ab/Cry1AcZM and the expression product of the constructed vector according to the disclosure have a killing effect on lepidopteran pests.

Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.

Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the trig signal.

Abstract: An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain.

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.

Abstract: An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.

Abstract: A built-in-self-test (BIST) circuit is connected to a processor and a sigma-delta modulator (SDM) and includes an averaging circuit, a reference signal generator, and a comparator. The averaging circuit calculates an average of a sum of a set of bit signals of the SDM output signal over a period of time period, and generates an average SDM signal. The reference signal generator generates a reference SDM signal based on an SDM input signal. The comparator compares the voltage levels of the average SDM and reference SDM signals with a threshold value, and generates a test output signal based on the comparison.

Abstract: An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the trig signal.

Abstract: An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain.