Patents by Inventor Wanggen Zhang
Wanggen Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9551749Abstract: Test circuitry for an integrated circuit (IC) that has a scan chain includes a control unit for applying a test pattern and a clock signal to the scan chain, and for varying the level of a supply voltage during a scan test procedure. In a first test phase, the supply voltage is set to the rated voltage level of the IC while a test pattern is shifted into the scan chain at a fast rate. A second, capture phase is run at a lower rate and the supply voltage is reduced to a lower level such that defects that cannot be detected when the capture phase is run at the rated voltage are observable yet switching elements in the IC still function correctly. Running the shift phase at the higher speed reduces the overall test time compared with known very low voltage (VLV) scan test procedures.Type: GrantFiled: June 18, 2015Date of Patent: January 24, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Wanggen Zhang, Huangsheng Ding, Jianzhou Wu
-
Publication number: 20160365157Abstract: An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.Type: ApplicationFiled: November 20, 2015Publication date: December 15, 2016Inventors: WEIWEI SANG, WANGGEN ZHANG
-
Publication number: 20160178695Abstract: Test circuitry for an integrated circuit (IC) that has a scan chain includes a control unit for applying a test pattern and a clock signal to the scan chain, and for varying the level of a supply voltage during a scan test procedure. In a first test phase, the supply voltage is set to the rated voltage level of the IC while a test pattern is shifted into the scan chain at a fast rate. A second, capture phase is run at a lower rate and the supply voltage is reduced to a lower level such that defects that cannot be detected when the capture phase is run at the rated voltage are observable yet switching elements in the IC still function correctly. Running the shift phase at the higher speed reduces the overall test time compared with known very low voltage (VLV) scan test procedures.Type: ApplicationFiled: June 18, 2015Publication date: June 23, 2016Inventors: WANGGEN ZHANG, HUANGSHENG DING, JIANZHOU WU
-
Publication number: 20150323590Abstract: An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.Type: ApplicationFiled: November 26, 2014Publication date: November 12, 2015Inventors: Xiuqiang Xu, Yin Guo, Shayan Zhang, Wanggen Zhang, Xu Zhang, Yizhong Zhang
-
Patent number: 9110133Abstract: A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.Type: GrantFiled: May 14, 2014Date of Patent: August 18, 2015Assignee: FREESCALE SEMICONDUCOTR, INC.Inventors: Ling Wang, Huangsheng Ding, Shayan Zhang, Wanggen Zhang
-
Publication number: 20150143587Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.Type: ApplicationFiled: January 16, 2015Publication date: May 21, 2015Inventors: Anisha Akula, David R. Duncan, Brenda A. Lowe, Michael T. Mann, William L. Petersen, Jyoti R. Rout, David D. Songstad, Joel B. Wilks, Wanggen Zhang
-
Patent number: 8962326Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.Type: GrantFiled: July 18, 2013Date of Patent: February 24, 2015Assignee: Monsanto Technology LLCInventors: Anisha Akula, David R. Duncan, Brenda A. Lowe, Michael T. Mann, William L. Petersen, Jyoti R. Rout, David D. Songstad, Joel B. Wilks, Wanggen Zhang
-
Publication number: 20150048863Abstract: A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.Type: ApplicationFiled: May 14, 2014Publication date: February 19, 2015Inventors: Ling Wang, Huangsheng Ding, Shayan Zhang, Wanggen Zhang
-
Patent number: 8935584Abstract: A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.Type: GrantFiled: November 19, 2012Date of Patent: January 13, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Guoping Wan, Shayan Zhang, Wanggen Zhang
-
Patent number: 8880965Abstract: A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.Type: GrantFiled: November 21, 2012Date of Patent: November 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Wanggen Zhang, Sian Lu, Shayan Zhang
-
Patent number: 8736302Abstract: A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.Type: GrantFiled: September 11, 2012Date of Patent: May 27, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Xu Zhang, Chad J. Lerma, Kai Liu, Sian Lu, Hao Wang, Shayan Zhang, Wanggen Zhang
-
Publication number: 20140059717Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.Type: ApplicationFiled: July 18, 2013Publication date: February 27, 2014Applicant: Monsanto Technology LLCInventors: Anisha Akula, David R. Duncan, Brenda A. Lowe, Michael T. Mann, William L. Petersen, Jyoti R. Rout, David D. Songstad, Joel B. Wilks, Wanggen Zhang
-
Publication number: 20140040688Abstract: A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.Type: ApplicationFiled: November 21, 2012Publication date: February 6, 2014Inventors: Wanggen Zhang, Sian Lu, Shayan Zhang
-
Publication number: 20140032986Abstract: A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.Type: ApplicationFiled: November 19, 2012Publication date: January 30, 2014Inventors: Guoping WAN, Shayan ZHANG, Wanggen ZHANG
-
Publication number: 20130300497Abstract: A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.Type: ApplicationFiled: September 11, 2012Publication date: November 14, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Xu Zhang, Chad J. Lerma, Kai Liu, Sian Lu, Hao Wang, Shayan Zhang, Wanggen Zhang
-
Patent number: 8513016Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.Type: GrantFiled: January 20, 2012Date of Patent: August 20, 2013Assignee: Monsanto Technology LLCInventors: Anisha Akula, David R. Duncan, Brenda A. Lowe, Michael T. Mann, William L. Petersen, Jyoti R. Rout, David D. Songstad, Joel B. Wilks, Wanggen Zhang
-
Patent number: 8415527Abstract: The present invention has incorporated a non-lethal negative selectable marker gene into the vector backbone DNA of a DNA plasmid used to transform plant cells. These transgenes are designed to express a non-lethal gene product in plant cells that contain the vector backbone DNA of the DNA plasmid. The gene products of the non-lethal negative selectable marker gene are involved in plant hormone biosynthesis pathways, plant hormone substrate diversion, plant hormone degradation, plant hormone signaling or metabolic interference. The use of these DNA plasmids to transform plant cells provides for the enhanced production of commercially viable plants.Type: GrantFiled: August 17, 2009Date of Patent: April 9, 2013Assignee: Monsanto Technology LLCInventors: Larry A. Gilbertson, Elysia K. Krieger, Wanggen Zhang, Xudong Ye
-
Publication number: 20120180166Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.Type: ApplicationFiled: January 20, 2012Publication date: July 12, 2012Inventors: Anisha Akula, David R. Duncan, Brenda A. Lowe, Michael T. Mann, William L. Petersen, Jyoti R. Rout, David D. Songstad, Joel B. Wilks, Wanggen Zhang
-
Patent number: 8124411Abstract: A method of producing a stably transformed corn plant in a single container is demonstrated. This method allows for the automation of the transformation process and reduces labor, material, and ergonomic costs associated with traditional plant tissue culture systems.Type: GrantFiled: August 31, 2007Date of Patent: February 28, 2012Assignee: Monsanto Technology LLCInventors: Anisha Akula, David R. Duncan, Brenda A. Lowe, Michael T. Mann, William L. Petersen, Jyoti R. Rout, David D. Songstad, Joel B. Wilks, Wanggen Zhang
-
Publication number: 20090328253Abstract: The present invention has incorporated a non-lethal negative selectable marker gene into the vector backbone DNA of a DNA plasmid used to transform plant cells. These transgenes are designed to express a non-lethal gene product in plant cells that contain the vector backbone DNA of the DNA plasmid. The gene products of the non-lethal negative selectable marker gene are involved in plant hormone biosynthesis pathways, plant hormone substrate diversion, plant hormone degradation, plant hormone signaling or metabolic interference. The use of these DNA plasmids to transform plant cells provides for the enhanced production of commercially viable plants.Type: ApplicationFiled: August 17, 2009Publication date: December 31, 2009Inventors: Larry A. Gilbertson, Elysia K. Krieger, Wanggen Zhang, Xudong Ye