Patents by Inventor Wangyang Zhang

Wangyang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240020573
    Abstract: Aspects of the disclosure are directed to an approach for extending forecasting models to various levels of granularity. The approach can include receiving a target level of granularity for distributing a forecast, performing forecast modeling at an aggregated level of granularity, and determining a distribution method to distribute results of the forecast model at the target level of granularity. The approach can improve performance over existing forecasting models with minimal overhead.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Inventors: Wangyang Zhang, Leyou Zhang, Rajarishi Sinha, Michael Peter Perrone, Andrew James McGehee, Dawei Jia, Jingtao Wang
  • Publication number: 20230354789
    Abstract: An indirect selective breeding method of high-collagen meat geese includes : (1) obtaining a curve equation y=0.017x+0.026; (2) rearing goslings to young geese; (3) measuring the length, width, and height values of the knobs of the geese, and calculating to give the collagen content according to the curve equation obtained in step (1); (4) sorting the geese in descending order according to the collagen content and keeping the geese with collagen content ranked top 50% as breeding geese; (5) after the geese lay eggs, hatching the goose eggs into goslings; and (6) repeating steps (2)-(5) for selective breeding over generations. The indirect selective breeding method is simple and easy to implement. A new strain of meat geese with high collagen content can be obtained from selective breeding simply by measuring the length, width, and height of the knobs of geese of each generation.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 9, 2023
    Applicant: YANGZHOU UNIVERSITY
    Inventors: Yu ZHANG, Qi XU, Yang ZHANG, Zhengfeng CAO, Wangyang JI, Zhixiu WANG, Guohong CHEN, Wenming ZHAO
  • Publication number: 20230297899
    Abstract: A method for optimal time-to-event (TTE) modeling includes obtaining a forecast request requesting performance of a TTE forecast forecasting an amount of time an event will occur after a starting point in time. The method includes obtaining a cutoff value representing an amount of time after the starting point in time that the event has not occurred. The method also includes forecasting, using an uncertainty forecasting model, the amount of time the event will occur after the starting point in time and updating the forecasted amount of time based on the cutoff value. The method also includes returning the updated forecasted amount of time the event will occur after the starting point in time.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 21, 2023
    Applicant: Google LLC
    Inventors: Jingtao Wang, Wangyang Zhang, Michael Peter Perrone
  • Patent number: 11562110
    Abstract: A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 24, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Hongzhou Liu, Hua Luo, Elias Lee Fallon
  • Patent number: 11544574
    Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 3, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Elias Lee Fallon
  • Patent number: 11275882
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and analyzing, via machine learning, at least one schematic feature from a pair of devices associated with the electronic design schematic. Embodiments may further include determining, based, at least in part, upon the analyzing, whether the pair of devices should be grouped together.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: March 15, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Elias Lee Fallon, Regis R. Colwell, Hua Luo, Namita Bhushan Rane
  • Patent number: 11087060
    Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second electronic design schematic or a second electronic design layout, wherein one or more hard constraints or one or more soft constraints or both are created, based upon, at least in part, the model.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 10, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Elias Lee Fallon, Regis R. Colwell, Hua Luo, Namita Bhushan Rane, Sheng Qian
  • Patent number: 11048852
    Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 29, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Elias Lee Fallon, Wangyang Zhang, Sheng Qian
  • Patent number: 11003825
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saleha Khatun, Sheng Qian, Wangyang Zhang, Elias Lee Fallon
  • Patent number: 10949596
    Abstract: Embodiments may include receiving an unplaced layout associated with an electronic circuit design and one or more grouping requirements. Embodiments may further include identifying instances that need to be placed at the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may also analyzing one or more instances that need to be placed at the unplaced layout and the one or more areas of the unplaced layout configured to receive the one or more instances. Embodiments may further include determining a location and an orientation for each of the one or more instances based upon, at least in part, the analyzing. Embodiments may also include generating a placed layout based upon, at least in part, the determined location and orientation for each of the one or more instances. Embodiments may further include during the generation of the placed layout, routing the placed layout.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 16, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Hua Luo, Regis R. Colwell, Qian Xu
  • Patent number: 10909293
    Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 2, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Hongzhou Liu, Richard J. O'Donovan, Michael Tian
  • Patent number: 10853550
    Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 1, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Hongzhou Liu, Richard J. O'Donovan, Michael Tian
  • Patent number: 10776548
    Abstract: A method for determining the tail performance of an integrated circuit is described. The method includes simulating the integrated circuit over samples to obtain values for circuit specifications and sorting the circuit specifications based on an expected number of samples. The method also includes arranging a sequence of samples from the universe according to a sequence in the group of circuit specifications, simulating the integrated circuit with one of the sequence of samples to obtain at least one circuit specification, removing the at least one circuit specification from the group when it satisfies the stop criterion, and modifying a model for a second circuit specification based on the at least one circuit specification. The computer-implemented method also includes reordering the group of circuit specifications based on the model and determining an integrated circuit performance based on a simulation result for the at least one circuit specification.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: September 15, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Wangyang Zhang
  • Patent number: 10747936
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a two stage routing analysis, wherein a first stage analysis is an intra-row routing analysis and a second stage is an inter-row routing analysis. Embodiments may also include generating an optimized routing of the one or more nets and displaying the optimized routing at a graphical user interface.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 18, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hua Luo, Regis R. Colwell, Wangyang Zhang
  • Patent number: 10699051
    Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations. An improved approach to perform cross-validations is provided.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 30, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Regis Colwell, Hua Luo, Namita Rane, Elias L. Fallon
  • Patent number: 10628546
    Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Regis Colwell, Wangyang Zhang, Elias L. Fallon, David White, Jose A. Martinez, Rong Chang Yan
  • Patent number: 10528644
    Abstract: A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations of the IC design, wherein the low yield values are estimated using Kernel Density Estimation, and the high yield values are estimated using repeated binary search. The cumulative distribution function and probability density function for a performance of the IC design are estimated based on the additional yield values and the additional specification values. Also, the method includes obtaining a quantile representation for the performance of the IC design from the cumulative distribution function.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 7, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Wangyang Zhang, Hongzhou Liu
  • Patent number: 10325056
    Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: June 18, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Wangyang Zhang, Hongzhou Liu
  • Patent number: 10289764
    Abstract: Methods and systems are provided. In one aspect, a method for parallel extraction of worst case corners of a number of electronic design automation (EDA) simulations includes generating multiple initial EDA simulation results for a number of specifications of an integrated circuit based on a first algorithm. For each specification, a respective first set of input samples is generated based on a second algorithm using generated multiple initial simulation results. Using a third algorithm, two or more of the respective first set of input samples are merged based on a criterion to generate a respective second set of input samples. For each specification, a first set of simulation results is generated using the respective second set of input samples. The worst case corners for the specifications are determined by applying in parallel local optimization to the first set of simulation results.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Wangyang Zhang
  • Patent number: 10275555
    Abstract: Method for estimating a yield of a post-layout circuit design is provided. In one aspect, a method includes obtaining a first pre-layout parameter and a second pre-layout parameter from pre-layout simulation samples of a circuit. The method also modeling a prior distribution of a first post-layout parameter and a second post-layout parameter based on the first pre-layout parameter, the second pre-layout parameter, a first hyper-parameter, and second hyper-parameter. The method further includes calculating the first hyper-parameter and the second hyper-parameter using a cross-validation, obtaining the first post-layout parameter and the second post-layout parameter based on the first hyper-parameter and the second hyper-parameter and estimating the yield of the circuit design using a non-normal distribution parameterized by the obtained first post-layout parameter and second post-layout parameter.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 30, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Wangyang Zhang, Shikha Sharma, Hongzhou Liu