Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.

Abstract: Methods and systems are provided. In one aspect, a method for parallel extraction of worst case corners of a number of electronic design automation (EDA) simulations includes generating multiple initial EDA simulation results for a number of specifications of an integrated circuit based on a first algorithm. For each specification, a respective first set of input samples is generated based on a second algorithm using generated multiple initial simulation results. Using a third algorithm, two or more of the respective first set of input samples are merged based on a criterion to generate a respective second set of input samples. For each specification, a first set of simulation results is generated using the respective second set of input samples. The worst case corners for the specifications are determined by applying in parallel local optimization to the first set of simulation results.

Abstract: Method for estimating a yield of a post-layout circuit design is provided. In one aspect, a method includes obtaining a first pre-layout parameter and a second pre-layout parameter from pre-layout simulation samples of a circuit. The method also modeling a prior distribution of a first post-layout parameter and a second post-layout parameter based on the first pre-layout parameter, the second pre-layout parameter, a first hyper-parameter, and second hyper-parameter. The method further includes calculating the first hyper-parameter and the second hyper-parameter using a cross-validation, obtaining the first post-layout parameter and the second post-layout parameter based on the first hyper-parameter and the second hyper-parameter and estimating the yield of the circuit design using a non-normal distribution parameterized by the obtained first post-layout parameter and second post-layout parameter.

Abstract: A method for determining mismatch variation of circuit components in a circuit is provided. The method includes determining a mismatch contribution for a specification of an integrated circuit design and displaying a list of components in the circuit design sorted according to the mismatch contribution. The method also includes displaying an adjustable scale for a size of the component, modifying the circuit design according to with the size of the component adjusted according to a user input to the adjustable scale, determining an adjusted mismatch contribution of the component, and displaying in the list of components a modified value of the mismatch contribution, and a modified value of an overall standard deviation for the specification in the circuit design.

Abstract: A system, method, and computer program product for reducing the number of Monte Carlo simulation samples required to determine if a design meets design specifications. The worst sample for each specification acts as a design corner to substitute for a full design verification. Embodiments determine the maximum number of samples needed, perform an initial performance modeling using an initial set of samples, and estimate the failure probability of each of the remaining samples based on the performance model. Embodiments then simulate remaining samples with a computer-operated Monte Carlo circuit simulation tool in decreasing design specification model accuracy order, wherein the sample predicted most likely to fail each specification is simulated first. Re-use of simulation results progressively improves models. Probability based stop criteria end the simulation early when the worst samples have been confidently found. A potential ten-fold reduction in overall specification verification time may result.

Abstract: A system, method, and computer program product for efficiently finding the best Monte Carlo simulation samples for use as design corners for all design specifications to substitute for a full circuit design verification. Embodiments calculate a corner target value matching an input variation level by modeling the circuit performance with verified accuracy, estimate the corner based on a response surface model such that the corner has the highest probability density (or extrapolation from the worst sample if the model is inaccurate), and verify and/or adjust the corner by performing a small number of additional simulations. Embodiments also estimate the probability that a design already meets the design specifications at a specified variation level. Composite multimodal and non-Gaussian probability distribution functions enhance model accuracy. The extracted design corners may be of particular utility during circuit design iterations.

Abstract: A system, method, and computer program product for automatically reducing the number of Monte Carlo simulation samples required to determine if a design yield is above or below a given yield target with a given confidence. Embodiments perform an initial Monte Carlo based performance modeling using an initial set of statistical samples, and estimate the failure probability of each of the remaining statistical samples based on the performance model. Embodiments then simulate each of the remaining statistical samples with a computer-operated Monte Carlo circuit simulation tool in decreasing failure probability order, wherein the sample most likely to fail is simulated first. Progressive comparisons of the simulated yield against a yield target eventually verify the yield at a required confidence level, halting the simulation and triggering tangible output of the comparison results. A potential ten-fold decrease in overall yield verification time without loss of accuracy may result.

Abstract: A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type of devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. When the samples exceed the mismatch parameters, a linear model is solved by least squares. Otherwise, a linear model is solved by orthogonal matching pursuit (OMP), and if that solution is too inaccurate then a new mixed method builds a better linear model. If the linear solution is too inaccurate, a full linear and quadratic model is made using OMP to select the most important variables, and the full model is fitted using OMP with selected cross terms. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions.

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. An ordered metric allocates output variance contributions for each input mismatch parameter in a linear model. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions. Additional sensitivity analysis can derive a final accurate linear contribution. Embodiments can reduce required simulations by a factor of ten.

Abstract: A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.