Patents by Inventor Wanki Kim

Wanki Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164628
    Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Wanki Kim, Stephen W. Bedell, Devendra K. Sadana
  • Patent number: 11133180
    Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 28, 2021
    Assignee: Lam Research Corporation
    Inventors: Hu Kang, Shankar Swaminathan, Jun Qian, Wanki Kim, Dennis M. Hausmann, Bart J. van Schravendijk, Adrien LaVoie
  • Publication number: 20210288250
    Abstract: A phase change memory (PCM) structure configured for performing a gradual reset operation includes first and second electrodes and a phase change material layer disposed between the first and second electrodes. The PCM structure further includes a thermal insulation layer disposed on at least sidewalls of the first and second electrodes and phase change material layer. The thermal insulation layer is configured to provide non-uniform heating of the phase change material layer. Optionally, the thermal insulation layer may be formed as an air gap. The PCM structure may be configured having the first and second electrodes aligned in a vertical or a lateral arrangement.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Ning Li, Wanki Kim, Devendra K. Sadana
  • Publication number: 20210267242
    Abstract: One aspect of the present disclosure relates to a granular composition containing sugar alcohols and a method for preparing the same. More specifically, according to one aspect of the present disclosure, a granular composition having a particle size of 12 mesh to 60 mesh may be prepared by introducing raw materials containing a high content of sugar alcohols containing (i) xylitol and (ii) erythritol, mannitol or a combination thereof to an extrusion molding granular, and the granular composition has a softly melting texture and has an excellent effect in user's preference and convenience in ingestion.
    Type: Application
    Filed: February 2, 2021
    Publication date: September 2, 2021
    Applicant: AMOREPACIFIC CORPORATION
    Inventors: Sukyung Kim, Juyeon Seo, Jinoh Chung, Wanki Kim, Chan Woong Park, Jaehyun Kim, Hyoseung Lee
  • Publication number: 20210264978
    Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Inventors: Ning Li, Wanki Kim, Stephen W. Bedell, Devendra K. Sadana
  • Publication number: 20210213777
    Abstract: A medical apparatus according to an embodiment of the present invention includes: a medical device; and a plurality of caster units, disposed below the medical device, for supporting the medical device to be movable, wherein each of the plurality of caster units includes: a wheel part; and a shock absorbing member which is configured to support the wheel part and to absorb the shock applied to the wheel part, wherein the shock absorbing member includes: a wheel fixing member for fixing the wheel part; a body fixing member which surrounds the wheel fixing member and is fixed to the medical device; and a cushioning member which is disposed between the wheel fixing member and the body fixing member and is capable of elastic deformation, wherein the shock absorbing member includes: a first deforming part extending in the vertical direction; and a second deformation part extending, from an end of the first deformation part, in a direction different from the extending direction of the first deformation part.
    Type: Application
    Filed: November 28, 2018
    Publication date: July 15, 2021
    Inventors: Yoenho Kim, Namyun Kim, Wanki Kim, Sungtae Sim, Junyoung Jung, Wonchul Choi
  • Patent number: 11055459
    Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Qianwen Chen, Li-Wen Hung, Wanki Kim, John U. Knickerbocker, Kenneth P. Rodbell, Robert L. Wisnieff
  • Patent number: 10997321
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Patent number: 10971546
    Abstract: A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fabio Carta, Matthew J. BrightSky, Bahman Hekmatshoartabari, Asit Ray, Wanki Kim
  • Publication number: 20210050384
    Abstract: A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Fabio Carta, Matthew J. BrightSky, Bahman Hekmatshoartabari, Asit Ray, Wanki Kim
  • Patent number: 10892413
    Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Fabio Carta, Wanki Kim, Chung H. Lam
  • Publication number: 20200411757
    Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Inventors: Wanki Kim, Fabio Carta, Chung H. Lam, Robert L. Bruce
  • Patent number: 10832773
    Abstract: A system includes an analog memory architecture for performing differential reading. The analog memory architecture includes a weight array including first cross-point devices located at intersections of a first set of conductive column wires and a first set of conductive row wires, and a reference array operatively coupled to the weight array and including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires. The second cross-point devices include differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seyoung Kim, Tayfun Gokmen, Nanbo Gong, Wanki Kim
  • Patent number: 10825514
    Abstract: The embodiments described herein facilitate performing bipolar switching of a confined phase change memory (PCM) with a metallic liner, wherein the phase change memory and the metallic liner are located between a first electrode and a second electrode of a semiconductor structure, wherein a first voltage is applied to the first electrode while the second electrode is grounded, and wherein a second voltage is applied to the second electrode while the first electrode is grounded. The bipolar switching can be performed so as to produce a plurality of resistance states. Thus, this confined PCM can be utilized as a multi-level cell (MLC) memory.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wanki Kim, Matthew Joseph BrightSky, Yu Zhu, Yujun Xie
  • Patent number: 10692574
    Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Wanki Kim, Chung Hon Lam, Yu Zhu, Yujun Xie
  • Publication number: 20200019732
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Publication number: 20200019731
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Publication number: 20190325954
    Abstract: The embodiments described herein facilitate performing bipolar switching of a confined phase change memory (PCM) with a metallic liner, wherein the phase change memory and the metallic liner are located between a first electrode and a second electrode of a semiconductor structure, wherein a first voltage is applied to the first electrode while the second electrode is grounded, and wherein a second voltage is applied to the second electrode while the first electrode is grounded. The bipolar switching can be performed so as to produce a plurality of resistance states. Thus, this confined PCM can be utilized as a multi-level cell (MLC) memory.
    Type: Application
    Filed: April 20, 2018
    Publication date: October 24, 2019
    Inventors: Wanki Kim, Matthew Joseph BrightSky, Yu Zhu, Yujun Xie
  • Publication number: 20190311082
    Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.
    Type: Application
    Filed: June 6, 2019
    Publication date: October 10, 2019
    Inventors: Qianwen Chen, Li-Wen Hung, Wanki Kim, John U. Knickerbocker, Kenneth P. Rodbell, Robert L. Wisnieff
  • Publication number: 20190311897
    Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.
    Type: Application
    Filed: May 31, 2019
    Publication date: October 10, 2019
    Inventors: Hu Kang, Shankar Swaminathan, Jun Qian, Wanki Kim, Dennis M. Hausmann, Bart J. van Schravendijk, Adrien LaVoie