Abstract: A channel structure includes a first patterned channel layer including a lower portion and an upper portion. The upper portion is disposed on the lower portion. A width of the upper portion is larger than a width of the lower portion. A material or a material composition ratio of the upper portion is different from a material or a material composition ratio of the lower portion. The height and the channel length of the channel structure are increased by disposing the first patterned channel layer, and the saturation current (Isat) of a transistor including the channel structure of the present invention may be enhanced accordingly.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a source layer; removing part of the source layer to form a first opening; forming a first channel layer in the first opening; forming a gate layer around the first channel layer and on the source layer; forming a drain layer on the gate layer and the first channel layer; removing part of the drain layer to form a second opening; and forming a second channel layer in the second opening.

Abstract: A semiconductor device is disclosed, including a plurality of gate rings formed on a substrate and concentrically surrounding a first doped region formed in the substrate. The gate rings are equipotentially interconnected by at least a connecting structure. A second doped region is formed in the substrate, exposed from the space between adjacent gate rings. A third doped region is formed in the substrate adjacent to the outer perimeter of the outermost gate ring. The first doped region, the third doped region and the gate rings are electrically biased and the second doped regions are electrically floating.

Abstract: A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract: There is set forth herein in one embodiment a semiconductor structure having a first region and a second region. The first region can include fins of a first fin height and the second region can include fins of a second fin height.

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract: An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Abstract: An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Abstract: Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

Abstract: A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract: One illustrative method disclosed herein includes, among other things, forming first, second and third fins that are arranged side-by-side, forming a recessed layer of insulating material in a plurality of trenches, after recessing the layer of insulating material, masking the first and second fins while exposing a portion of the axial length of the second fin, removing the exposed portion of the second fin so as to thereby define a cavity in the recessed layer of insulating material, forming an SDB isolation structure in the cavity, wherein the SDB isolation structure has an upper surface that is positioned above the recessed upper surface of the recessed layer of insulating material, removing the masking layer, and forming a gate structure for a transistor above the SDB isolation structure.

Abstract: Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

Abstract: A method for forming FinFETs with reduced series resistance includes providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate, a gate disposed over a first portion of the fin, and a first sidewall spacer disposed over the fin and adjacent to the gate, increasing epitaxially the thickness of a second portion of the fin disposed outside the gate and the first sidewall spacer, and forming a second sidewall spacer disposed over the second portion of the fin and adjacent to the first sidewall spacer. A thickness of the second portion of the fin disposed under the second spacer is equal to or greater than a thickness of the first portion of the fin disposed under the gate.

Abstract: Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.