Abstract: In some embodiments, a system includes a first memory assembly coupled to a first channel and a second memory assembly coupled to a second channel. The system includes a memory controller to write first and second primary data sections to the first and second memory assemblies, respectively, and write first and second redundant data sections to the second and first memory assemblies, respectively, wherein the first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

Abstract: A method and system of managing resources in a host bridge by determining whether resources are deficient, preventing a second device from obtaining further resources and if this measure does not enable a first device to obtain resources, guaranteeing all resources to the first device.

Abstract: The disclosure presents a device comprising a driver configured to transmit a signal on a bus line, including a driver element configured to pull against termination impedance. The impedance of the driver element is dynamically adjustable. The disclosure also presents a method of electronically adjusting the impedance of the driver element to regulate the swing voltage on the bus line.

Abstract: A bus bridging method, a bus bridge and a bus agent are described. In a bus agent provides to a bus bridge a read data request targeting a data source bridged by the bus bridge. The read data request includes a read address indicating a starting storage location of the requested data, and a read size indicator indicating the size of the requested data. The bus bridge, in response, facilitates provision of the requested data to the bus agent. The facilitation includes streaming buffered ones of the requested data to the bus agent through one or more successive streaming connections to the bus bridge by the bus agent.

Abstract: A method includes transmitting packets on a bus and maintaining a number of the packets in-flight on the bus according to a number of active streams for the bus.

Abstract: A method is provided for recovering the effective address of memory instructions in an out-of-order microprocessor for use by an exception handler upon the occurrence of one of an exception and a systems management interrupt. The microprocessor comprises at least one execution unit for executing a plurality of instructions out-of-order and a re-order buffer having storage locations for buffering result data produced from the execution of the plurality of instructions. Each instruction is associated with a location designator to identify a unique storage location within the re-order buffer in which the result data for an executed instruction is written. The microprocessor further comprises a memory order buffer having storage locations for buffering memory instructions waiting for access to memory for execution, these storage locations also being identified by corresponding location designators.

Abstract: A rounding mechanism and methodology, particularly useful for complex calculations involving multiple numeric operations (e.g., transcendentals) in which rounding performed on source operands, prior to their use in a current numeric operation, is used to determine the manner in which the result of the current numeric operation is rounded. Therefore, the result is rounded based on the rounding history of its source operands.