Patents by Inventor Wataru Uesugi

Wataru Uesugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9704562
    Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: July 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Kiyoshi Kato, Wataru Uesugi, Takahiko Ishizu
  • Patent number: 9704882
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Publication number: 20170194048
    Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.
    Type: Application
    Filed: March 21, 2017
    Publication date: July 6, 2017
    Inventors: Takahiko ISHIZU, Kiyoshi KATO, Tatsuya ONUKI, Wataru UESUGI
  • Publication number: 20170187360
    Abstract: A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.
    Type: Application
    Filed: December 21, 2016
    Publication date: June 29, 2017
    Inventors: Wataru UESUGI, Takeshi OSADA
  • Patent number: 9640255
    Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 2, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Wataru Uesugi
  • Patent number: 9627010
    Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: April 18, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Kiyoshi Kato, Tatsuya Onuki, Wataru Uesugi
  • Publication number: 20170062044
    Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 2, 2017
    Inventors: Takahiko ISHIZU, Wataru UESUGI, Kiyoshi KATO, Tatsuya ONUKI
  • Publication number: 20170005658
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 5, 2017
    Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
  • Patent number: 9536592
    Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: January 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoaki Tsutsui, Atsuo Isobe, Wataru Uesugi, Takuro Ohmaru
  • Publication number: 20160373089
    Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 22, 2016
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio MAEHASHI, Siichi YONEDA, Wataru UESUGI
  • Publication number: 20160351552
    Abstract: To provide a display device which includes a touch sensor and a large number of pixels and in which a driver circuit of a display portion and a driver circuit of a touch sensor are formed in one IC. The display device includes the display portion, the touch sensor, and a plurality of ICs. The plurality of ICs each include a first circuit. One of the plurality of ICs includes a second circuit and a third circuit. The first circuit has a function of outputting a video signal to the display portion. The second circuit has a function of outputting a signal for driving a sensor element included in the touch sensor. The third circuit has a function of converting an analog signal output from the sensor element into a digital signal.
    Type: Application
    Filed: May 23, 2016
    Publication date: December 1, 2016
    Inventors: Kei TAKAHASHI, Wataru UESUGI, Hiromichi GODO
  • Publication number: 20160284407
    Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.
    Type: Application
    Filed: March 28, 2016
    Publication date: September 29, 2016
    Inventors: Tatsuya ONUKI, Wataru UESUGI
  • Patent number: 9454923
    Abstract: A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor. A channel formation region of the transistor is included in an oxide semiconductor film.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: September 27, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidetomo Kobayashi, Kiyoshi Kato, Wataru Uesugi
  • Patent number: 9443564
    Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 13, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Wataru Uesugi, Kiyoshi Kato, Tatsuya Onuki
  • Patent number: 9438206
    Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio Maehashi, Seiichi Yoneda, Wataru Uesugi
  • Patent number: 9438234
    Abstract: A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a second circuit. The pair of retention circuits includes two switches electrically connected to each other in series and a capacitor electrically connected to a connection portion of the two switches. Each of the two switches is formed using an oxide semiconductor transistor. The first circuit has a function of generating complementary data from a piece of input data. The pair of retention circuits retains the complementary data. The second circuit has a function of amplifying the complementary data retained in the pair of retention circuits.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: September 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Yukio Maehashi, Wataru Uesugi
  • Publication number: 20160233866
    Abstract: A semiconductor device with lower power consumption and an electronic device including the same are provided. To reduce leakage current flowing in a word line driver circuit, a switching element is provided, specifically, between the word line driver circuit and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the word line driver circuit. Furthermore, to reduce the stand-by power due to precharge of a bit line, a switching element is provided in a bit line driver circuit, specifically, between the bit line and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the bit line driver circuit.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 11, 2016
    Inventors: Takahiko ISHIZU, Wataru UESUGI
  • Publication number: 20160217848
    Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 28, 2016
    Inventors: Takahiko ISHIZU, Wataru UESUGI, Kiyoshi KATO, Tatsuya ONUKI
  • Publication number: 20160203852
    Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 14, 2016
    Inventors: Naoaki TSUTSUI, Atsuo ISOBE, Wataru UESUGI, Takuro OHMARU
  • Patent number: 9385713
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: July 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe