Abstract: A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a second circuit. The pair of retention circuits includes two switches electrically connected to each other in series and a capacitor electrically connected to a connection portion of the two switches. Each of the two switches is formed using an oxide semiconductor transistor. The first circuit has a function of generating complementary data from a piece of input data. The pair of retention circuits retains the complementary data. The second circuit has a function of amplifying the complementary data retained in the pair of retention circuits.

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

Abstract: The power consumption of a semiconductor device that can function as a latch circuit or the like is reduced. The semiconductor device includes a first circuit and a switch that controls conduction between an input terminal and the first circuit. The first circuit includes n second circuits (n is an integer of 2 or more) and a variable resistor. An output node of any of the n second circuits is electrically connected to an input node of the second circuit in a first stage through the variable resistor. The variable resistor can be, for example, a transistor whose channel is formed in an oxide semiconductor layer. A reduction in the number of elements or signals leads to a reduction of the power consumption of the semiconductor device.

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract: To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node.

Abstract: A semiconductor device with a novel structure is provided. In the semiconductor device executing a pipeline processing, a first arithmetic unit and a second arithmetic unit are provided for an execution stage, and transistors for performing power gating for the respective arithmetic units are provided. Only the arithmetic unit that performs an arithmetic operation is supplied with power supply voltage. Thus, fine-grained power gating can be performed, so that the power consumption of the semiconductor device can be reduced. In each of the transistors for performing power gating, a channel formation region includes an oxide semiconductor; thus, a reduction in leakage current between power supply lines can be achieved. Furthermore, these transistors and transistors in the arithmetic units can be provided in different layers, and thus an increase in area overhead due to the additionally provided transistors can be prevented.

Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

Abstract: The power consumption of a semiconductor device that can function as a latch circuit or the like is reduced. The semiconductor device includes a first circuit and a switch that controls conduction between an input terminal and the first circuit. The first circuit includes n second circuits (n is an integer of 2 or more) and a variable resistor. An output node of any of the n second circuits is electrically connected to an input node of the second circuit in a first stage through the variable resistor. The variable resistor can be, for example, a transistor whose channel is formed in an oxide semiconductor layer. A reduction in the number of elements or signals leads to a reduction of the power consumption of the semiconductor device.

Abstract: To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal.

Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

Abstract: A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor. A channel formation region of the transistor is included in an oxide semiconductor film.

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract: To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node.

Abstract: To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal.

Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.