Abstract: Disclosed herein are antenna systems, methods, and devices. The device includes a first portion including a first antenna array; and a second portion including a second antenna array, wherein the first portion and the second portion are movable with respect to one another, and wherein the first antenna array and the second antenna array are arranged such that in a first relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate in combination with one another, and in a second relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate independently of one another.

Abstract: A wireless communication device can include chains of circuitry, with at least one chain being a chain of transmitter circuitry to generate output radio frequency (RF) signals using baseband signals and at least one chain of receiver circuitry configured to receive RF signals. At least one chain can include a plurality of circuit blocks, a circuit block including at least one of oscillator circuitry, clocking circuitry, and phased lock loop (PLL) circuitry. The apparatus can include interconnect circuitry configured to couple one of the plurality of circuit blocks to a respective chain. Other systems, methods and apparatuses are described.

Abstract: A wireless communication device can include modem circuitry to connect the UE to a repeater over a side-link connection. The device can also include processing circuitry to control a repeater beamforming process to select a beam angle from the repeater to a base station and initiate a communication procedure using the selected beam angle. Other methods, systems and apparatuses are described.

Abstract: A power amplifier circuit including a plurality of analog power amplifiers configured to generate a output power for an output signal; at least one processor configured to: select a highest output power signal; determine an input signal power of a modulated signal; determine an output signal power based on the input signal power; compare the output signal power and the highest output power; and disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.

Abstract: A wireless communication device can include an oscillator circuit. The oscillator circuit can include an oscillator and measurement circuitry coupled to the oscillator. The measurement circuitry can receive an output signal of the oscillator and measure oscillator error by comparing the output signal of the oscillator to a nominal frequency for an amount of time. The oscillator circuit can further include adjustment circuitry to adjust an oscillator frequency of the oscillator based on the measured oscillator error.

Abstract: Disclosed herein is an apparatus of a radio communication device, where the apparatus may include a plurality of signal paths, each signal path of the plurality of signal paths is configured to receive a radio frequency, RF, signal from a corresponding RF circuit. The apparatus may also include a processor configured to determine first signal paths and a second signal path from the plurality of signal paths, wherein the first signal paths are configured to receive first RF signals of the RF signals. The processor may also be configured to demodulate the first RF signals received from the first signal paths to decode received communication data; perform, for a frequency band, an RF environmental sensing operation based on a digital signal converted from a second RF signal of the RF signals, wherein the second RF signal is provided by the second signal path.

Abstract: This disclosure describes systems, methods, and devices for placing bits in an isochronous data stream from a first data port to a second data port. A device may inject, using a first port, based on a periodicity less than a defined frame rate of a data stream comprising multiple frames, a status or control bit in place of one or more low-order bits, reserved bits, or unused bits of a frame of the data stream, wherein the frame includes one or more data words; receive, using a second port synchronized to the periodicity, the data stream from the first port; extract, using the second port, based on the periodicity, the status or control bit; and extract, using the second port, a remainder of the frame.

Abstract: An apparatus for controlling an equalizer is provided. The apparatus comprises interface circuitry configured to receive at least one of an input signal and an output signal of the equalizer. The apparatus further comprises processing circuitry configured to determine at least one signal metric based on the at least one of the input signal and the output signal of the equalizer, select an operating mode of the equalizer from a plurality of different operating modes based on the determined signal metric, and control the equalizer to operate in the selected operating mode.

Abstract: Methods and devices configured to determine, for a slot including a plurality of symbols allocated for downlink data, a downlink data block allocation scheme with a number of blocks of downlink data that remain constant or monotonically decrease starting at a designated symbol of the plurality of symbols allocated for downlink data; generate a voltage profile corresponding to the downlink data block allocation scheme, where the voltage profile includes a plurality of bias voltages; and apply a bias voltage selected from the plurality of bias voltages to a power amplifier in a transmission chain of the base station.

Abstract: Disclosed herein are antenna systems, methods, and devices. The device includes a first portion including a first antenna array; and a second portion including a second antenna array, wherein the first portion and the second portion are movable with respect to one another, and wherein the first antenna array and the second antenna array are arranged such that in a first relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate in combination with one another, and in a second relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate independently of one another.

Abstract: Systems, apparatuses, methods, and computer-readable media are provided for managing operations associated with multi-device serial read for communication buses. Embodiments include a protocol controller coupled to a transmitter and receiver assembly of a device to control the transmitter and receiver assembly to perform a multi-device read protocol to read from a plurality of devices coupled to the serial bus using a single device group read command. Other embodiments may be described and/or claimed.

Abstract: A wireless communication device can include modem circuitry to connect the UE to a repeater over a side-link connection. The device can also include processing circuitry to control a repeater beamforming process to select a beam angle from the repeater to a base station and initiate a communication procedure using the selected beam angle. Other methods, systems and apparatuses are described.

Abstract: A wireless communication device can include an oscillator circuit. The oscillator circuit can include an oscillator and measurement circuitry coupled to the oscillator. The measurement circuitry can receive an output signal of the oscillator and measure oscillator error by comparing the output signal of the oscillator to a nominal frequency for an amount of time. The oscillator circuit can further include adjustment circuitry to adjust an oscillator frequency of the oscillator based on the measured oscillator error.

Abstract: A wireless communication device can include chains of circuitry, with at least one chain being a chain of transmitter circuitry to generate output radio frequency (RF) signals using baseband signals and at least one chain of receiver circuitry configured to receive RF signals. At least one chain can include a plurality of circuit blocks, a circuit block including at least one of oscillator circuitry, clocking circuitry, and phased lock loop (PLL) circuitry. The apparatus can include interconnect circuitry configured to couple one of the plurality of circuit blocks to a respective chain. Other systems, methods and apparatuses are described.

Abstract: A power amplifier circuit including a plurality of analog power amplifiers configured to generate a output power for an output signal; at least one processor configured to: select a highest output power signal; determine an input signal power of a modulated signal; determine an output signal power based on the input signal power; compare the output signal power and the highest output power; and disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.

Abstract: In a communication device and corresponding methods, a hierarchical, reduced power, beam search process includes a hierarchical activation of the radio frequency frontend (RFFE), transceiver, and baseband integrated circuit (BBIC) for a beam searching operations. For example, a first signal metric measurements can be performed to determine signal information. An operating mode can be determined based on the signal information. In a first operating mode, one or more second signal metric measurements can be performed for a subset of beamforming configurations of the wireless communication device to determine beamforming information. In a second operating mode, one or more third signal metric measurements can be performed on the beamforming configurations to determine the beamforming information.

Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

Abstract: In a communication device and corresponding methods, a hierarchical, reduced power, beam search process includes a hierarchical activation of the radio frequency frontend (RFFE), transceiver, and baseband integrated circuit (BBIC) for a beam searching operations. For example, a first signal metric measurements can be performed to determine signal information. An operating mode can be determined based on the signal information. In a first operating mode, one or more second signal metric measurements can be performed for a subset of beamforming configurations of the wireless communication device to determine beamforming information. In a second operating mode, one or more third signal metric measurements can be performed on the beamforming configurations to determine the beamforming information.

Abstract: Systems, apparatuses, methods, and computer-readable media are provided for managing operations associated with multi-device serial read for communication buses. Embodiments include a protocol controller coupled to a transmitter and receiver assembly of a device to control the transmitter and receiver assembly to perform a multi-device read protocol to read from a plurality of devices coupled to the serial bus using a single device group read command. Other embodiments may be described and/or claimed.

Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.