Abstract: Techniques described herein manage failed storage devices. A number of failed storage devices is determined to exceed a number of redundancies in a storage configuration of the storage system. The status of a failed storage device is changed to permit solely read operations. Valid data from the failed storage device is copied to a spare storage device. Invalid data on the failed storage device is reconstructed based on corresponding data from other storage devices, and the reconstructed data is stored on the spare storage device. The failed storage device is removed from the storage system.

Abstract: In aspects of flip position detection, a mobile device has a device housing with a base section and a flip section that folds onto the base section. The mobile device has a hinge that operates between open and closed positions of the device, and the flip section of the device housing operates to open relative to the base section of the device housing. An inductor is positioned in the device housing to have an inductance as the hinge operates to open and close the device housing. A metal plate is coupled to the hinge in a configuration that translates the metal plate relative to the inductor as the hinge operates between the open and closed positions. A sensor is implemented to detect the inductance between the inductor and the metal plate, where inductance values indicate the closed and open positions of the device housing.

Abstract: In aspects of flip position detection, a mobile device has a device housing with a base section and a flip section that folds onto the base section. The mobile device has a hinge that operates between open and closed positions of the device, and the flip section of the device housing operates to open relative to the base section of the device housing. An inductor is positioned in the device housing to have an inductance as the hinge operates to open and close the device housing. A metal plate is coupled to the hinge in a configuration that translates the metal plate relative to the inductor as the hinge operates between the open and closed positions. A sensor is implemented to detect the inductance between the inductor and the metal plate, where inductance values indicate the closed and open positions of the device housing.

Abstract: The system and method provide establishment of hooks in a send-path at inter-object interfaces of a layered stack of the storage driver and hooks in the completion-path execution sequence of storage driver of a storage system, the completion-path hook inserts replacement storage response messages to simulate the specified storage access error.

Abstract: Described are techniques for performing a firmware update. A drive management object determines one or more physical drives matching criteria of a first received request. The drive management object sends to provision drive objects a second request to update firmware on physical drives. Firmware update processing is performed independently for each physical drive. Each provision drive object is associated with one of the physical drives. Firmware update processing for said one physical drive includes determining whether to perform the firmware update at a current point in time; in response to determining to perform the firmware update at the current point in time, performing preparation processing; notifying, upon completion of said preparation processing, a physical drive object associated with said one physical drive to download the firmware update to the one physical drive; and resuming I/O operations to the one physical drive upon successfully completing the firmware update.

Abstract: Described are techniques for performing a firmware update. A drive management object determines one or more physical drives matching criteria of a first received request. The drive management object sends to provision drive objects a second request to update firmware on physical drives. Firmware update processing is performed independently for each physical drive. Each provision drive object is associated with one of the physical drives. Firmware update processing for said one physical drive includes determining whether to perform the firmware update at a current point in time; in response to determining to perform the firmware update at the current point in time, performing preparation processing; notifying, upon completion of said preparation processing, a physical drive object associated with said one physical drive to download the firmware update to the one physical drive; and resuming I/O operations to the one physical drive upon successfully completing the firmware update.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.

Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

Abstract: A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.

Abstract: A system including an integrated circuit memory device. The integrated circuit device comprises a register to store a value representative of an output voltage setting. A circuit holds a value representative of an adjustment to the output voltage setting. An output driver outputs a drive voltage during a calibration operation, wherein a signal is generated based on a comparison between a signal derived from the drive voltage and a reference voltage. The signal updates the value representative of the adjustment to the output voltage setting.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

Abstract: A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode.

Abstract: A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.