Abstract: An interference determining method, includes: obtaining first frequency information of a first resource; obtaining second frequency information of a second resource, where a frequency indicated by the first frequency information is lower than a frequency indicated by the second frequency information; determining, based on the first frequency information, harmonic frequency information corresponding to the first resource; and determining, based on the harmonic frequency information and the second frequency information, harmonic interference information between the first resource and the second resource.

Abstract: Disclosed herein are new radio (NR) Data link architecture options including, for example, NR radio bearer models, NR logical channel models, and MAC and HARQ models. Further described are packet flows mapping to data radio bearers (DRBs), and a new flow encapsulation protocol in the user plane. In some embodiments, DRBs with different quality of service (QoS) are pre-established, but not activated. This allows a given user equipment (UE) to use these DRBs for packet data network (PDN) flows without a large overhead. Pre-established DRBs can be an extension to default bearer concept with the decision of pre-establishment of DRBs based on UE capability, subscription profile, operation policy, installed apps, etc.

Abstract: An encapsulating structure to protect an image sensor chip at all times during manufacture and use includes a printed circuit board, an image sensor chip, a protecting sheet, and a package portion. The image sensor chip is mounted on the printed circuit board and the protecting sheet is mounted on the image sensor chip. The package portion is entirely opaque and is formed on the printed circuit board, the package portion encloses side wall of the image sensor chip, the protecting sheet, and portion of surface of the protecting sheet away from the image sensor chip. A method for manufacturing same is also disclosed.

Abstract: The disclosure provides a water cooling radiator including cold end chamber body, thermoelectric chip, heat dissipating assembly and water tank. The thermoelectric chip has cooling surface and heat-generating surface, and the cooling surface is thermally coupled to the cold end chamber body. The dissipating assembly is thermally coupled to the heat-generating surface. The water tank has first chamber, second chamber, outer inlet, first inner outlet, first inner inlet and outer outlet. The cold end chamber body has a channel, two opposite ends of the channel are respectively connected to the first inner outlet and the first inner inlet, allowing liquid coolant flowing into the first chamber via the outer inlet to flow through the channel and then flow out of the second chamber from the outer outlet.

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract: A slide rail assembly includes a first rail, a second rail, a first locking mechanism, a second locking mechanism, and an operating member. The second rail can be displaced with respect to the first rail. The first locking mechanism and the second locking mechanism are configured to keep the second rail at either of two predetermined positions. The operating member can be used to operate the first locking mechanism and the second locking mechanism and thereby bring the locking mechanisms from a locked state to an unlocked state.

Abstract: The control device includes a touch sensor circuit, a control circuit, a driving circuit and a switching circuit. The touch sensor circuit is configured to generate a touch signal and a function signal in response to a touch state of a touch component. The control circuit is activated by a first voltage. The control circuit selectivity generates a self-holding signal according to the function signal when it is activated. The driving circuit is configured to generate a drive signal according to the touch signal or the self-holding signal. The switch circuit is turned on by the drive signal so as to provide the first voltage to the control circuit by the turned-on switching circuit. When the control circuit generated the self-holding signal, the control circuit is configured to continuously transmit the self-holding signal to the driving circuit according to the function signal during a first enabling period.

Abstract: An encapsulation structure to protect an image sensor chip at all times during manufacture and use includes a printed circuit board, an image sensor chip, a supporting portion, a protecting film and a package portion. The image sensor chip is mounted on the printed circuit board and the supporting portion is mounted on the printed circuit board to surround the image sensor chip. The package portion is entirely opaque and is formed on the printed circuit board, the package portion encloses side wall of the supporting portion and the protecting film, and portion of surface of the protecting sheet away from the image sensor chip.

Abstract: Methods, systems, and devices may assist in reducing signaling load that occur based on paging and handover. Methods, systems, and devices may be based on UE states, a radio access network registration area (RRA) or tracking/paging area with different architectural approaches (e.g., hierarchical or distributed), dynamic RRA management, radio access network based paging, and radio access network based user equipment (UE) mobility management.

Abstract: An apparatus includes a first metrology tool configured to measure an initial thickness of a wafer. The apparatus includes a controller connected to the first metrology tool and configured to calculate a polishing time based on a material removal rate, a predetermined thickness and the initial thickness of the wafer. The apparatus includes a polishing tool connected to the controller and configured to polish the wafer for a first duration equal to the polishing time. The apparatus includes a second metrology tool connected to the controller and configured to measure a polished thickness. The controller is configured for receiving the initial thickness from the first metrology tool and the polished thickness from the second metrology tool, updating the material removal rate based on the predetermined thickness, the polishing time and the polished thickness, and calculating an etching time for etching the polished wafer using the polished thickness.

Abstract: The present application relates to a system and method for driving a three-color and four-color pixel display panel, including: providing a three-color pixel display panel; connecting the three-color pixel display panel to a driver; generating, by the driver, a fourth color sub-pixel according to grayscale values of three color sub-pixels to convert the three-color pixel display panel to a four-color pixel display panel; converting, by the driver, each two adjacent pixel units to one pixel unit, and each two adjacent fourth color sub-pixels to one fourth color sub-pixel; and converting, by the driver, each fourth color sub-pixel back to the first color sub-pixel, the second color sub-pixel and the third color sub-pixel, so as to convert the four-color pixel display panel back to the three-color pixel display panel.

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

Abstract: This disclosure relates to nanoparticles coated with fusion proteins comprising a domain that binds a cancer marker and a domain comprising a toxic polypeptide. In certain embodiments, the targeted cancer marker is urokinase plasminogen activator receptor (uPAR) insulin-like growth factor 1 receptor (IGF1R), EGFR, HER2, and/or other member of the ErbB family of receptors. In certain embodiments, the molecule that binds a cancer marker is an amino terminal fragment of uPA or variant capable of binding uPAR and/or IGF1 or variant capable of binding IGF1R. In certain embodiments, the toxic polypeptide is a bacterial exotoxin.

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Abstract: A system for transmitting data over an optical communication path is configured to receive data to be encoded in a bitstream for transmission using an optical communication path and encodes the received data to obtain a bitstream. The system is further configured to determine that the bitstream includes a sequence of consecutive bits, and obtain a power level at which to transmit a portion of the bitstream based on a count of the consecutive bits in the sequence. The system may be configured to selectively activate a light source at a power level according to a modulation scheme to optically transmit the portion of the bitstream at the power level.

Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

Abstract: An electronic device may include a display. The display may be formed by an array of light-emitting diodes mounted to the surface of a substrate. The substrate may be a silicon substrate. Circuitry may be located in spaces between the light-emitting diodes. Circuitry may also be located on the rear surface of the silicon substrate and may be coupled to the array of light-emitting diodes using through-silicon vias. The circuitry may include integrated circuits and other components that are attached to the substrate and may include transistors and other circuitry formed within the silicon substrate. Touch sensor electrodes, light sensors, and other components may be located in the spaces between the light-emitting diodes. The substrate may be formed from a transparent material that allows image light to reach a lens and image sensor mounted below the substrate.

Abstract: A system for transmitting data over an optical communication path is configured to receive data to be encoded in a bitstream for transmission using an optical communication path and encodes the received data to obtain a bitstream. The system is further configured to determine that the bitstream includes a sequence of consecutive bits, and obtain a power level at which to transmit a portion of the bitstream based on a count of the consecutive bits in the sequence. The system may be configured to selectively activate a light source at a power level according to a modulation scheme to optically transmit the portion of the bitstream at the power level.