Patents by Inventor Wei A. Chen

Wei A. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10717745
    Abstract: The present disclosure is directed to compounds of Formula (I) and methods of their use and preparation, as well as compositions comprising compounds of Formula (I).
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 21, 2020
    Assignee: Janssen Pharmaceutica NV
    Inventors: Nidhi Arora, Genesis M. Bacani, Joseph Kent Barbay, Scott D. Bembenek, Min Cai, Wei Chen, Charlotte Pooley Deckhut, James P. Edwards, Brahmananda Ghosh, Kevin D. Kreutter, Gang Li, Mark S. Tichenor, Jennifer D. Venable, Jianmei Wei, John J. M. Wiener, Yao Wu, Kun Xiao, Feihuang Zhang, Yaoping Zhu
  • Patent number: 10718224
    Abstract: An aft frame assembly has a main body with an upstream facing surface, a downstream facing surface, a radially outer facing surface and a radially inner facing surface. Feed hole inlets are located on the upstream facing surface and radially outward of the outer sleeve so that the feed hole inlets are located to receive input from a high pressure plenum. The feed hole inlets are coupled to cooling channels that pass through the main body. Microchannels are formed in or near the radially inner facing surface and the downstream facing surface. The cooling channels are connected to and terminate in the microchannels. Exit holes are connected to the plurality of microchannels, and the exit holes are located radially outward of the transition piece and radially inward of the outer sleeve. The exit holes are located to exhaust into the cooling annulus.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 21, 2020
    Assignee: General Electric Company
    Inventors: Charles Lewis Davis, III, Kevin Weston McMahan, Wei Chen, Scott Robert Simmons
  • Patent number: 10718187
    Abstract: A method for selecting a bottomhole assembly (BHA) includes inputting BHA parameters, wellbore parameters, and drilling operating parameters, performing a dynamic simulation of a first BHA based on the BHA parameters, wellbore parameters, and drilling operating parameters, and presenting a wellbore quality factor of the first BHA calculated from the dynamic simulation.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 21, 2020
    Assignee: SMITH INTERNATIONAL, INC.
    Inventors: Yuelin Shen, Wei Chen, Zhengxin Zhang, Jibin Shi, Riadh Boualleg, Sujian Huang
  • Patent number: 10720569
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Johnathan D. Harms
  • Patent number: 10720385
    Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Publication number: 20200227471
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 16, 2020
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Publication number: 20200228681
    Abstract: A method for color correction includes obtaining a noise evaluation image and a corrected noise evaluation image, determining a peak signal-to-noise ratio (PSNR) difference by comparing the noise evaluation image and the corrected noise evaluation image, obtaining a downsampled noise evaluation image and a downsampled corrected noise evaluation image, determining a downsampled PSNR difference by comparing the downsampled noise evaluation image and the downsampled corrected noise evaluation image, and determining a noise amplification metric based on a weighted average of the PSNR difference and the downsampled PSNR difference.
    Type: Application
    Filed: February 6, 2020
    Publication date: July 16, 2020
    Inventors: Wei CHEN, Zisheng CAO
  • Publication number: 20200222601
    Abstract: A blood separation method is provided. The blood separation method includes the following steps. Firstly, a whole blood is placed in a container having a separating gel, which includes a silicon-containing polymer, and a specific gravity of the separating gel is between 1.030 and 1.093. Then, a centrifugation is performed at a first effective rotation speed to divide the whole blood into a red blood cell layer located below the separating gel, a buffy coat layer located above the separating gel, and a plasma layer located above the buffy coat layer. The buffy coat layer and the plasma layer are then mixed to obtain a platelet-rich plasma.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 16, 2020
    Inventors: DAI-JEN LEE, SHIH-WEI CHEN
  • Publication number: 20200225396
    Abstract: A polarizing sheet includes a base layer, and a polarizing layer attached to the base layer. The polarizing layer includes, in a same plane, a combination of any two or more of a first region, a second region, or a third region. The first region, the second region and the third region have different light transmission properties.
    Type: Application
    Filed: August 29, 2019
    Publication date: July 16, 2020
    Applicant: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
    Inventors: Wei CHEN, Zhiwen XU, Jiwei CHEN
  • Publication number: 20200225877
    Abstract: There is provided with an information processing apparatus. A control unit controls writing of weight data to a first memory and a second memory, and controls readout of the weight data from the first memory and the second memory. The control unit further switches an operation between a first operation in which a processing unit reads out first weight data from the first memory and performs the convolution operation processing using the first weight data while the processing unit writes second weight data to the second memory in parallel, and a second operation in which the processing unit reads out the first weight data from both the first memory and the second memory and performs the convolution operation processing using the first weight data.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 16, 2020
    Inventors: Daisuke Nakashima, Tse-Wei Chen
  • Publication number: 20200228515
    Abstract: Disclosed are embodiments to improve security of authentication credentials. In some aspects, a client device, upon which authentication credentials may be entered cooperates with a server device, which may provide authentication services, to obscure delays between characters of the authentication credentials. This reduces the ability of a nefarious actor to surreptitiously obtain the delays, which may compromise security of a computer account when these delays are used as a signature of a user login process.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 16, 2020
    Inventors: Amer A. Hassan, Russell Andrew Penar, Wei-Chen Chen
  • Publication number: 20200227120
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.
    Type: Application
    Filed: March 5, 2019
    Publication date: July 16, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
  • Publication number: 20200227269
    Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 16, 2020
    Inventors: Wei-Hsin Liu, Ta-Wei Chiu, Chia-Lung Chang, Po-Chun Chen, Hong-Yi Fang, Yi-Wei Chen
  • Publication number: 20200227264
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20200224866
    Abstract: Provided is an intelligently-connected vehicle LED headlight using graphene, which comprises an imaging lens assembly (9, 5, 6, 7), an LED light source (1), and a heat dissipation assembly (2, 3, 4), wherein the imaging lens assembly (9, 5, 6, 7) is connected to the LED light source (1), and the LED source (1) is connected to the heat dissipation assembly (2, 3, 4). The light distribution manner of the light source of the vehicle headlight is changed from emitting light by a reflector to emitting light by imaging, so that the light emission efficiency is improved by more than 30%. Further, a graphene heat dissipation material is used in the vehicle headlight to dissipate heat, and accordingly the heat dissipation capability of the lamp can be better improved, thereby prolonging the service life of the vehicle headlight.
    Type: Application
    Filed: July 27, 2018
    Publication date: July 16, 2020
    Inventors: Wei CHEN, Wei JIANG, LiBin ZHOU
  • Publication number: 20200227310
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material, wherein the through-via has an end. The end of the through-via is tapered and has rounded sidewall surfaces. The package further includes a redistribution line electrically coupled to the through-via.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventor: Hsien-Wei Chen
  • Patent number: 10715172
    Abstract: Disclosed is an analog-to-digital converter with an adjustable operation frequency for noise reduction. The operation frequency of the analog-to-digital converter is adjustable, and if an input signal or a circuit is affected by a noise, the noise can be reduced by spreading the frequency distribution of the noise. A clock generator generates a clock signal for controlling the operation frequency of the analog-to-digital converter. Additionally, a clock controller receives a setting signal and a counting signal, controls the clock generator, and adjusts the frequency of the clock signal. In addition, a counter counts the number of periods of the clock signal, and generates the counting signal. Furthermore, a selecting signal makes the frequency of the clock signal gradually increase or decrease with time, thereby allowing change rate or change amount of the frequency of the clock signal to be adjustable.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 14, 2020
    Assignee: HYCON TECHNOLOGY CORP
    Inventors: Po-Yin Chao, Hung-Wei Chen, Shui-Chu Lee
  • Patent number: 10714442
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10712782
    Abstract: A front cover assembly includes a frame, a cover glass, and a waterproof glue. The frame has a receiving cavity. The cover glass is partially received in the frame. The cover glass has a lateral face facing the frame. The cover glass has a step portion located at the lateral face. A first gap is defined between a first face of the step portion of the cover glass and a first wall of the frame, and a second gap is defined between a second face of the step portion of the cover glass and a second wall of the frame. A waterproof glue fills the first and second gaps. The first and second faces of the step portion from an obtuse angle therebetween, which faces the first and second walls of the frame. The present disclosure also relates to a terminal.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 14, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Yimei Tang, Yong Li, Hong Zou, Yi Sun, Wei Zhang, Xinfeng Liao, Zhiqin Hu, Xiaohui Wang, Bing Liu, Yuchu Xu, Wei Chen
  • Patent number: D890261
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: July 14, 2020
    Inventor: Wei Chen