Patents by Inventor Wei-An Lin

Wei-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Publication number: 20240136299
    Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
  • Publication number: 20240133018
    Abstract: A metal mask includes: a mask body having two opposite first side edges along a first direction and two opposite second side edges along a second direction, and each of the first side edges having a first length. The mask body includes an open slot region, two first fixing regions, and two first clamping regions, where the two first fixing regions are positioned on two opposite sides of the open slot region, respectively, and each of the first clamping regions is positioned between each of the first fixing regions and each of the first side edges. A first gap is formed in each of the first side edges, the first gap has a first opening length in the first direction, and a ratio of the first opening length to the first length being between 0.2 and 0.8. The metal mask may improve the problem of wrinkles.
    Type: Application
    Filed: March 22, 2023
    Publication date: April 25, 2024
    Inventors: YunPei Yang, Chi-Wei Lin
  • Publication number: 20240131538
    Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 25, 2024
    Inventors: CHEN-CHUNG DU, Ming-Jyh Chang, Chang-Yi Chen, Ming-Hau Tsai, Ko-Chieh chao, Yi-Wei Lin
  • Publication number: 20240132667
    Abstract: Provided is a polyamide foam molded body and method for manufacturing the same. The method includes performing polymerization with a monomer composition to form a polyamide terpolymer; mixing a supercritical carbon dioxide foaming agent and the polyamide terpolymer under a pressure to form a mixture; and releasing the pressure of the mixture to foam the polyamide terpolymer for forming the polyamide foam molded body. The monomer composition comprises 50 to 70 mole % of a caprolactam, 4 to 15 mole % of a polyetheramine, 4 to 15 mole % of a dicarboxylic acid and 15 to 30 mole % of a Nylon salt. The polyamide terpolymer includes a hard segment formed by the caprolactam, the dicarboxylic acid and the Nylon salt and a soft segment formed by the polyetheramine. The polyamide foam molded body exhibits excellent properties and is environmental-friendly.
    Type: Application
    Filed: September 7, 2023
    Publication date: April 25, 2024
    Inventors: Yi-Huan Lee, Chia-Hsing Lin, Chia-Wei Lee
  • Patent number: 11967168
    Abstract: A method and device of fingerprint image generation for saving memory. The method includes generating a first fingerprint image of an original data size according to a plurality of first analog sensing signals which are read from a fingerprint sensor array before an exposure period ends. Then the first fingerprint image represented by a first data size which is equivalent to or smaller than the original data size is stored. a second fingerprint image of the original data size is generated after generating the first fingerprint image of the original data size according to a plurality of second analog sensing signals which are read from the fingerprint sensor array during the exposure period. The second fingerprint image represented by a compressed data size smaller than the original data size is then stored.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: April 23, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Weilun Shih, Wu-Wei Lin
  • Patent number: 11966352
    Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: April 23, 2024
    Assignee: Dell Products L.P.
    Inventors: Yu-Feng Lin, Hao-Cheng Ku, Yi-Wei Lu
  • Patent number: 11966546
    Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: April 23, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Chen-Cheng Lin, Chia-I Liu, Kun-Hsien Lee, Hung-Wei Tseng
  • Patent number: 11967596
    Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 11968869
    Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: April 23, 2024
    Assignee: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Publication number: 20240128120
    Abstract: A package structure and a manufacturing method thereof are disclosed. The structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. The connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. The redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.
    Type: Application
    Filed: March 30, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Wei Liu, Chung-Kuang Lin
  • Publication number: 20240130220
    Abstract: Provided are organometallic compounds comprising iridium as a central metal atom which is coordinated by two three-dentate ligands which each comprise at least three 5-membered or 6-membered rings. Also provided are formulations comprising these organometallic compounds. Further provided are organic light emitting devices (OLEDs) and related consumer products that utilize these organometallic compounds.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 18, 2024
    Applicant: UNIVERSAL DISPLAY CORPORATION
    Inventors: Jui-Yi TSAI, Walter YEAGER, Henry Carl HERBOL, Harvey WENDT, Wei-Chun SHIH, Alexey Borisovich DYATKIN, Elena SHEINA, Chun LIN
  • Publication number: 20240127758
    Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.
    Type: Application
    Filed: May 23, 2023
    Publication date: April 18, 2024
    Inventors: Shinya Ono, Chin-Wei Lin, Chen-Ming Chen, Hassan Edrees
  • Publication number: 20240128313
    Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tse-Hsiao LIU, Chih-Wei LIN, Po-Hao CHIU, Pi-Kuang CHUANG, Ching-Yi HSU
  • Publication number: 20240128518
    Abstract: An electrode assembly and a lithium ion electric roll having the same are provided. The electrode assembly includes: a first electrode unit; a first anti-puncture cushion; in which the first electrode unit includes a first electrode sheet, an second electrode sheet, and a separator, the second electrode sheet comprises a second top edge and a second bottom edge along the length direction of the first electrode unit; an edge of the first anti-puncture cushion exceeds the second electrode sheet from the second top edge or the second bottom edge along the length direction of the first electrode unit.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Applicant: DONGGUAN AMPEREX TECHNOLOGY LIMITED
    Inventors: Junliang ZHU, Haibing WANG, Tongming DONG, Wenqiang CHENG, Baohua CHEN, Shufeng WU, Wei YANG, Zhihua QIN, Meina LIN
  • Publication number: 20240128142
    Abstract: The present application discloses a double-sided SiP packaging structure and a manufacturing method thereof, wherein the double-sided SiP packaging structure comprises a substrate, a first packaging structure arranged on the substrate, and a second packaging structure arranged below the substrate; the second packaging structure comprises a chip, interposer and a molding material; a conductive structure array is arranged on an upper surface of the interposer; the interposer is arranged below the substrate through the conductive structure array; a space region among a lower surface of the substrate, the chip and the interposer is filled with the molding material; a conductive bonding pad array is arranged on the lower surface of the interposer; and a groove is formed in a part of region between the conductive bonding pad and an edge contour of the interposer.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 18, 2024
    Applicant: JCET GROUP CO., LTD.
    Inventors: Shuo Liu, Yaojian Lin, Jianyong Wu, Wei Yan, Jing Zhao
  • Publication number: 20240128403
    Abstract: The present disclosure provides a micro light-emitting element, method for manufacturing a micro light-emitting element, and a light-emitting device. The micro light-emitting element includes a DBR structure layer, including a DBR adhesive layer, a DBR reflective layer, and a DBR sacrificial layer, where the DBR adhesive layer, the DBR reflective layer, and the DBR sacrificial layer are sequentially stacked. Subsequent structural coverage of a DBR reflective layer is improved by means of the DBR adhesion layer. Density of film layers of the DBR sacrificial layer, the DBR reflective layer, and the DBR adhesive layer are sequentially increased, so that etching rates of the DBR sacrificial layer, the DBR reflective layer, and the DBR adhesive layer are sequentially decreased during etching, thereby forming an inverted trapezoidal through hole which comprises an inclined side wall by an etching process.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Applicant: XIAMEN CHANGELIGHT CO., LTD.
    Inventors: Wei LIU, Weiwen LIU, Shaowen PENG, Fengjie LIN, Hongyi ZHOU
  • Publication number: 20240123434
    Abstract: A multifunctional catalyst, a method for producing the same, and a method for using the same are provided. The multifunctional catalyst is applicable for recycling a polyester fabric. The multifunctional catalyst includes a carrier, and a first functional ionic liquid and a second functional ionic liquid that are grafted on the carrier. The carrier is an inorganic composite powder material, and is composed of following chemical components: C: Na—Ni/Al2O3. In a process of recycling the polyester fabric, the multifunctional catalyst simultaneously decolorizes and depolymerizes the polyester fabric. The first functional ionic liquid is used to decolorize the polyester fabric, and the second functional ionic liquid is used to depolymerize the polyester fabric.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 18, 2024
    Inventors: TE-CHAO LIAO, WEI-SHENG CHENG, YU-LIN LI
  • Publication number: 20240127754
    Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 18, 2024
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Shih Chang Chang, Shinya Ono
  • Patent number: D1024055
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Hsueh-Wei Chung, Pao-Ching Huang, Cheng-Han Lin