Patents by Inventor Wei An

Wei An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11032864
    Abstract: A method and device are disclosed from the perspective of a first device handling radio link failure. In one method, the method includes the first device performing or establishing sidelink unicast communication with a second device. The method also includes the first device performing or establishing sidelink unicast communication with a third device. The method also includes the first device detecting a radio link failure associated with the second device. The method further includes the first device performing a Sidelink MAC reset associated with the second device in response to the radio link failure, and not performing a Sidelink MAC reset associated with the third device.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: June 8, 2021
    Assignee: ASUSTek Computer Inc.
    Inventors: Yi-Hsuan Kung, Li-Chih Tseng, Chun-Wei Huang, Ming-Che Li, Li-Te Pan
  • Patent number: 11032636
    Abstract: A speaker module includes a housing and a speaker unit accommodated in the housing. The housing includes a bottom wall, a top wall, and a side wall. The speaker module further includes at least one first isolating member connected to the bottom wall and the top wall respectively. The first isolating member isolates an accommodating space into an accommodating cavity and a first filling cavity. The first isolating member includes a first metal frame and an air-permeable isolating mesh attached to the first metal frame. The first metal frame includes a first top border and a first bottom border. The first top border and/or the first bottom border is provided with a protrusion portion, and the protrusion portion abuts against the top wall or the bottom wall and is connected to the top wall or the bottom wall by spot welding.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 8, 2021
    Assignee: AAC Technologies Pte. Ltd.
    Inventors: Zhichen Chen, Wei Wei
  • Patent number: 11031290
    Abstract: A semiconductor structure with cutting depth control and method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, fins protruding from a substrate are formed. Next, source/drain devices are grown on both ends of the fins. Then, an inter-layer dielectric layer crossing the fins and enclosing the source/drain devices is deposited. A metal gate structure enclosed by the inter-layer dielectric layer is formed between the source/drain devices. And then, a replacement operation is performed to replace a portion of the inter-layer dielectric layer with an isolation material, thereby forming an isolation portion that adjoins the metal gate structure and is located between the adjacent source/drain devices. Thereafter, a metal gate cut operation is performed, thereby forming an opening in the metal gate structure and an opening in the isolation portion, and an insulating material is deposited in the openings.
    Type: Grant
    Filed: January 21, 2018
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Shu-Yuan Ku, I-Wei Yang, Yi-Hsuan Hsiao, Ming-Ching Chang, Ryan Chia-Jen Chen
  • Patent number: 11031303
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hung-Ling Shih, Tsung-Yu Yang, Yun-Chi Wu, Po-Wei Liu
  • Patent number: 11030366
    Abstract: A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram; and selecting one group (selected group) of the recurrent ad hoc groups such that: the cells in the selected group have connections representing a corresponding logic circuit; each cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of a corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma
  • Patent number: 11028970
    Abstract: An light bulb, comprising: a lamp housing with inner surface and outer surface opposite to the inner surface of the lamp housing, the lamp housing includes a layer of luminescent material, which is formed on the inner surface or the outer surface of the lamp housing or integrated in the material of the lamp housing; a bulb base connected to the lamp housing; a stem connected to the bulb base and located in the lamp housing; and a single filament, disposed in the light housing.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: June 8, 2021
    Assignee: ZHEJIANG SUPER LIGHTING ELECTRIC APPLIANCE CO., LTD
    Inventors: Tao Jiang, Wei-Hong Xu, Yukihiro Saito, Hayato Unagiike, Ai-Ming Xiong, Jun-Feng Xu, Yi-Ching Chen
  • Patent number: 11026947
    Abstract: The present invention provides small-molecule inhibitors of BMP signaling and compositions and methods for inhibiting BMP signaling. These compounds and compositions may be used to modulate cell growth, differentiation, proliferation, and apoptosis, and thus may be useful for treating diseases or conditions associated with BMP signaling, including inflammation, cardiovascular disease, hematological disease, cancer, and bone disorders, as well as for modulating cellular differentiation and/or proliferation. These compounds and compositions may also be used to treat subjects with Sjögren's syndrome, or diffuse intrinsic pontine glioma (DIPG).
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 8, 2021
    Assignees: The Brigham and Women's Hospital, Inc., The United States of America, as Represented by the Secretary, Dept, of Health and Human Services
    Inventors: Paul B. Yu, Wenwei Huang, Philip Edward Sanderson, Jian-Kang Jiang, Khalida Shamim, Wei Zheng, Xiuli Huang, Gregory Tawa, Arthur Lee, Asaf Alimardanov, Junfeng Huang
  • Patent number: 11027404
    Abstract: A power tool includes a housing having a motor housing portion and a front casing coupled to the motor housing portion. The power tool also includes an electric motor positioned within the motor housing portion, a drive assembly having an output shaft to which a tool element for performing work on a workpiece is attachable, and a powdered metal bushing disposed within the front casing that rotatably supports the output shaft.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 8, 2021
    Assignee: Milwaukee Electric Tool Corporation
    Inventors: Peter Malak, Michael R. Sande, Ryan Allen Dedrickson, Guang Hu, Fan Bin Zeng, Wei Chao Xu, Qiao Cai
  • Patent number: 11031926
    Abstract: A digital clock circuit is provided. The digital clock circuit includes a first sub-circuit comprising a first digitally-controlled oscillator driven by a frequency control word to control a first output frequency synthesized from multiple first pulses, and a first frequency divider to generate a trigger signal having a frequency equal to 1/M of the first output frequency. The digital clock circuit also includes a second sub-circuit comprising a loop of feedback including a frequency detector to compare an input frequency with a feedback frequency, a controller to adjust the frequency control word, a second digitally-controlled oscillator driven by the frequency control word plus a constant to control a second output frequency synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider to set the feedback frequency equal to 1/N of the second output frequency in the loop of feedback.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 8, 2021
    Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiangye Wei, Liming Xiu, Yiming Bai, Xin Li
  • Patent number: 11031508
    Abstract: A semiconductor device includes a source region, a drain region, a SiGe channel region, an interfacial layer, a high-k dielectric layer and a gate electrode. The source region and the drain region are over a substrate. The SiGe channel region is laterally between the source region and the drain region. The interfacial layer forms a nitrogen-containing interface with the SiGe channel region. The high-k dielectric layer is over the interfacial layer. The gate electrode is over the high-k dielectric layer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu Chang, Hsiang-Pi Chang, Zi-Wei Fang
  • Patent number: 11032472
    Abstract: An image-capturing device uses a light reflecting member to redirect an exterior light image toward a lens module in order to focus the light image onto an image-capturing unit. The image-capturing device includes a rotating unit for driving the light-reflecting member to rotate within a limited range in such a manner that the image-capturing device can capture at least two light images of different photo-ing areas and combine them into one single combined image without a need of moving the image-capturing unit and the lens module. When a user takes a panoramic or wide-ranged picture, he/she doesn't need to move the whole image-capturing device, but only needs to stand at the same position, faces the same direction and simply pushes the shutter button, and then the image-capturing device will automatically capture light images of different photo-ing areas and then integrate them into one single panoramic or wide-ranged picture.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 8, 2021
    Inventors: Chao Chang Hu, Chih Wei Weng
  • Patent number: 11031354
    Abstract: A method includes forming an interposer, which includes a semiconductor substrate, and an interconnect structure over the semiconductor substrate. The method further includes bonding a device die to the interposer, so that a first metal pad in the interposer is bonded to a second metal pad in the device die, and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die. The method further includes encapsulating the device die in an encapsulating material, forming conductive features over and electrically coupling to the device die, and removing the semiconductor substrate. A part of the interposer, the device die, and portions of the conductive features in combination form a package.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Chih-Chia Hu, Chen-Hua Yu
  • Patent number: 11028111
    Abstract: Provided are a compound for treating metabolic diseases having the structure as shown in formula (I) or formula (II), or a racemate, stereoisomer, geometric isomer, tautomer, solvate, hydrate, metabolite, pharmaceutically acceptable salt or prodrug thereof. The compound is an activator of FXR and/or a TGR5 receptor, and thus has the activity of activating FXR and/or a TGR5 receptor, and can be used in the preparation of drugs for treating chronic liver diseases, metabolic diseases or portal hypertension.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: June 8, 2021
    Assignee: XI' AN BIOCARE PHARMA LTD.
    Inventors: Guoqin Fu, Wei Ding, Bo Yin, Chao Yang, Cuiqin Wang, Yong Dou, Ruiling Wang
  • Patent number: 11032024
    Abstract: This application provides a radio fronthaul interface signal transmission method, a device, and a system. A network device obtains a radio fronthaul interface signal including a plurality of code blocks. The network device maps the radio fronthaul interface signal to M flexible Ethernet FlexE service layer timeslots to generate a FlexE signal, where the FlexE service layer timeslots are determined based on a rate of the radio fronthaul interface signal, and M is a positive integer greater than or equal to 1. The network device sends the FlexE signal to one or more physical lanes. The radio fronthaul interface signal such as a CPRI signal, an eCPRI signal, or an NGFI signal is carried by using FlexE, and the FlexE service layer timeslots are divided based on the rate of the radio fronthaul interface signal.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 8, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qiuyou Wu, Wei Su, Qiwen Zhong
  • Patent number: 11030130
    Abstract: A storage device including a memory array and a peripheral logic circuit is provided. The memory array includes a plurality of banks and a data path. The peripheral logic circuit operates in a copy mode or a normal mode according to a mode-switch command. In the copy mode, the peripheral logic circuit directs a first bank to provide specific data to the data path and directs a second bank to receive specific data from the data path.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 8, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Chih-Wei Liang
  • Patent number: 11032872
    Abstract: A method and an apparatus for deleting a session context are provided, to resolve a technical problem of how to delete an SM context from an SMF after abnormal network disconnection. The method includes: receiving, by a session management function entity, a packet data unit PDU session release request; and deleting, by the session management function entity based on the PDU session release request, a PDU session context that is stored in the session management function entity and that is of a terminal, where the PDU session context is a PDU session context that is not deleted after the terminal is abnormally deregistered.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 8, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Anni Wei, Yizhuang Wu, Chunshan Xiong
  • Patent number: 11031329
    Abstract: A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 8, 2021
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chu-Chin Hu, Shih-Ping Hsu, Che-Wei Hsu, Chin-Ming Liu, Chih-Kuai Yang
  • Patent number: 11032647
    Abstract: The disclosure relates to a multi-layered speaker cover for covering a speaker. The speaker cover has at least one first layer and a second layer, wherein the first layer is an air-permeable layer and the second layer is a layer with through-holes for reducing dynamic pressure.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: June 8, 2021
    Assignee: Audi AG
    Inventors: Simon Weiß, Manuel Wenzel
  • Publication number: 20210165888
    Abstract: A mechanism for augmenting security features associated with internet of things devices located in home and/or office environments is provided. A method can comprise as a function of retrieved data associated with a device, displaying vulnerability data associated with the device; facilitating downloading of resolution data to the device based on the vulnerability data; facilitating reconfiguring of the device based on the resolution data; and allocating reward data representative of a reward to a user device based on the reconfiguring of the device being determined to have completed.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Inventors: Wei Wang, Cristina Serban
  • Patent number: D922020
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 8, 2021
    Assignee: QINGDAO TMZ TOOLS CO., LTD
    Inventor: Wei Pang