Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state. The memory device also includes circuitry that is configured to determine that the memory cells have experienced significant read disturb. Without erasing the memory cells, the circuitry is further configured to program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.

Abstract: The present application relates to an adhesive applying apparatus, an adhesive applying method and a battery processing device. The adhesive applying apparatus includes a workbench, an adhesive applying mechanism, a detection assembly, and a visual compensation module. The detection assembly can detect to obtain current positions of a battery cell and adhesive paper respectively. The visual compensation module can obtain a total deviation value based on a deviation value between the current position of the battery cell and its target position and a deviation value between the current position of the adhesive paper and its target position, and then correct an adhesive applying position of the adhesive applying mechanism based on the total deviation value, so that the adhesive applying mechanism can apply adhesive on the battery cell at the corrected adhesive applying position, thereby effectively improving precision of adhesive applying for the battery cell.

Abstract: This patent document describes, among other things, techniques, and apparatuses for providing non-terrestrial network connectivity to improve wireless network efficiency and performance. In one aspect, a method of wireless communication is disclosed. The method includes transmitting, from a network node to a user device, a block of system information that includes system information that is time varying due to at least one of movement of the network node or movement of the user device.

Abstract: The memory device includes a plurality of programmed memory blocks containing data and at least one spare memory block that does not contain data. The memory device also includes control circuitry that is configured to perform a plurality of read operations on the programmed memory blocks. Without having reprogrammed the memory cells of any of the plurality of programmed memory blocks, the circuitry is configured to detect a trigger event. In response to detecting the trigger event, the circuitry is configured to relocate data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block so that the at least one spare memory block becomes a programmed memory block and then erase the selected memory block so that the selected memory block becomes a new spare memory block.

Abstract: To increase the speed of programming, a non-volatile memory system programs some word lines using a two pass programming process and other word lines using a one pass programming process.

Abstract: Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells. To further improve the number of current based data states that can be stored, a ground core structure within the insulating core can introduced along with memory cells with an increased channel length, such as by increasing the relative thickness of the word line layers or shorting together multiple word lines.

Abstract: The memory device includes a memory block with at least one drain-side select gate and an array of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line in a programming operation. In a programming pulse, the circuitry is configured to apply a select gate voltage VSGD to the at least one drain-side select gate, apply a bit line inhibit voltage VDDSA to a plurality of unselected bit lines, apply a very low voltage to a plurality of selected bit lines, and apply a programming voltage to a selected word line of the plurality of word lines. The bit line inhibit voltage VDDSA is no greater than 1.5 V.

Abstract: A memory device is provided that includes a memory block with an array of memory cells that are arranged in word lines, including a selected word line that is programmed according to a storage scheme that has at least three data states. The memory device further includes circuitry for reading the data of the selected word line. During a sensing operation, for a set duration, the circuitry discharges a sensing capacitor through a selected NAND string that includes a selected memory cell to be read. After discharging the sensing capacitor for the set duration, the circuitry conducts a first comparison of a voltage at a sense node to a trip voltage. The circuitry is further applies a first voltage to an opposite side of the sensing capacitor from the sense node and then conducts a second comparison of the voltage at the sense node to the trip voltage.

Abstract: Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells.

Abstract: The present invention relates to an indole carboxamide compound, preparation therefor and use thereof. The indole carboxamide is represented by the following general formula (I). The compound of the present invention is more stable and active and can be used for prophylaxis or treatment of nephropathy, sepsis, arthritis, pulmonary hypertension or tumor.

Abstract: Techniques are described to indicate characteristics (e.g., configuration related control information and/or scheduling related control information) of signals forwarded by a smart node to a base station (BS) and/or to a user equipment (UE). An example wireless communication method includes receiving, by a first network node from a second network node, a configuration information that configures the first network node, and transmitting, by the first network node to a communication node or to the second network node, a first signal comprising a first information according to the configuration information, where, prior to the transmitting, the first network node receives from the second network node or from the communication node a second signal comprising a second information that includes the first information.

Abstract: Provided are bispecific antibodies capable of binding to human VEGF protein and human PD-1 protein. These bispecific antibodies are effective in treating cancer.

Abstract: Systems, methods and apparatus for achieving a synchronization between a wireless device and a network device are described. One example method includes transmitting, by the wireless device to the network device, a first message indicating a property of a validity timer associated with a synchronization information determined by the wireless device.

Abstract: Presented are systems and methods for capacity expansion of control channel. A wireless communication device (e.g., UE) may receive a first indication of a physical uplink control channel (PUCCH) resource for PUCCH transmission from a wireless communication node (e.g., BS). The wireless communication device can determine the PUCCH resource to perform the PUCCH transmission.

Abstract: An apparatus is provided that includes a NAND string including a first memory cell coupled to a first word line, and a control circuit coupled to the NAND string. The control circuit is configured to apply a verify voltage to the first word line, perform a verify test on the first memory cell to sense a hole conduction current, and perform a program operation on the first memory cell without performing a pre-charge operation.

Abstract: Systems and methods for wireless communications are disclosed herein. In some embodiments, a wireless communication method includes applying, by a base station, code sequences or scrambling codes to repetitions of broadcast information of a plurality of resources of a cell of the base station. Each of the code sequence or the scrambling codes being specific to a corresponding one of the plurality of resources. Each of the plurality of resources is a beam of the cell. In addition, the base station transmits, to a wireless communication device, the repetitions of the broadcast information with the code sequences or the scrambling codes applied.

Abstract: The memory device includes a memory block with a source line, a plurality of bit lines, and an array of memory cells that are disposed between the source line and the plurality of bit lines. The memory cells are arranged in a plurality of word lines, which are divided into at least three sub-blocks including a source-side sub-block, a drain-side sub-block, and at least one middle sub-block. The memory device also includes circuitry for programming the memory cells of the memory block. The circuitry is configured to program the memory cells of the source-side sub-block and the drain-side sub-block to a first single-bit per memory cell (SLC) threshold voltage distribution that includes two data states. The circuitry is also configured to program the memory cells of the at least one middle sub-block to a second SLC threshold voltage distribution that is different than the first SLC threshold voltage distribution.

Abstract: The present application provides a bottom layer metal interconnection line structure, at least including a test key and leads connected to the test key; the test key being composed of a plurality of metal lines connected end-to-end; the plurality of metal lines being arranged in the same plane in a winding manner, wherein at least one suspending via structure is provided at each winding point; and two leads are provided and respectively connected to ends of the metal lines located at a head end and a tail end in the test key. The present application increases a maximum root-mean-square current that the winding metal interconnection lines can withstand while improving a heat dissipation problem of the bottom layer metal interconnection lines.

Abstract: The present invention provides an engineered immune cell targeting BCMA and use thereof. In particular, the present invention provides a CAR specifically targeting BCMA, the CAR comprising an antigen-binding domain which is an S-derived scFv, an antibody heavy chain variable region as shown in SEQ ID NO: 9 and an antibody light chain variable region as shown in SEQ ID NO: 10. The present invention also provides a CAR-T cell comprising the CAR, a double CAR- and CAR-T cell comprising the S-derived scFv, and related use thereof. Compared to CAR-T cells constructed using other scFvs, the constructed CAR-T cell of the present invention has a better killing effect and tumor elimination capability.

Abstract: A memory apparatus includes memory cells configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to detect whether data stored in a group of the memory cells as one bit per each of the memory cells has errors. The control means is also configured to bypass error correction of the data stored in the group of the memory cells in response to not detecting the errors in the data stored.