Patents by Inventor Wei-Chang Chen

Wei-Chang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953614
    Abstract: A method for measuring coordinate position include detecting the distance of a target relative to a portable electronic device to generate a measurement signal corresponding to the distance, sensing a relative position of the target to generate a azimuth angle corresponding to the relative position, detecting the movement of the portable electronic device to generate an inertial signal corresponding to the movement, obtaining positioning information of the portable electronic device, converting the measurement signal into distance data, converting the inertial signal into a tilt angle, calculating coordinate difference information with the tilt angle, the distance data and the azimuth angle, and calculating coordinate position of the target with the positioning information and the coordinate difference information.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: April 9, 2024
    Assignee: Getac Technology Corporation
    Inventors: Chia-Chang Chiu, Wei-Rong Chen
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Publication number: 20240069431
    Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.
    Type: Application
    Filed: February 16, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Che HSIEH, Chien-Cheng Chen, Ping-Hsun Lin, Ta-Cheng Lien, Hsin-Chang Lee
  • Publication number: 20240071888
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
  • Patent number: 11915942
    Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: D943594
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: February 15, 2022
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D948510
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 12, 2022
    Assignee: Acer Incorporated
    Inventors: Jung-Wei Tsao, Wei-Chang Chen, Ker-Wei Lin
  • Patent number: D948512
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: April 12, 2022
    Assignee: Acer Incorporated
    Inventors: Jung-Wei Tsao, Wei-Chang Chen
  • Patent number: D955400
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 21, 2022
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D989040
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 13, 2023
    Assignee: Acer Incorporated
    Inventors: Jung-Wei Tsao, Wei-Chang Chen
  • Patent number: D995482
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: August 15, 2023
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D1000444
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: October 3, 2023
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D1000980
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 10, 2023
    Assignee: Acer Incorporated
    Inventors: Jung-Wei Tsao, Ker-Wei Lin, Wei-Chang Chen
  • Patent number: D1001129
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: October 10, 2023
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D1006027
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 28, 2023
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D1012689
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 30, 2024
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D1016313
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D1016822
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 5, 2024
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao
  • Patent number: D1023378
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 16, 2024
    Assignee: Acer Incorporated
    Inventors: Wei-Chang Chen, Jung-Wei Tsao