Abstract: An antenna correcting system is provided. The antenna correction system compares amplitudes of antenna signals that are emitted or received respectively by a plurality of antenna units with each other to select one of the amplitudes as target amplitude. The antenna correction system corrects the amplitude of each of the antenna signals according to the target amplitude. As a result, the amplitudes of the antenna signals are the same as each other or approximate to each other. After the amplitudes of the antenna signals are corrected, the antenna correction system compares phases of the antenna signals with each other to select one of the phases as a target phase. The antenna correction system corrects the phase of each of the antenna signals according to the target phase. As a result, the phases of the antenna signals are the same as each other or approximate to each other.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.

Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

Abstract: A multifunctional catalyst, a method for producing the same, and a method for using the same are provided. The multifunctional catalyst is applicable for recycling a polyester fabric. The multifunctional catalyst includes a carrier, and a first functional ionic liquid and a second functional ionic liquid that are grafted on the carrier. The carrier is an inorganic composite powder material, and is composed of following chemical components: C: Na—Ni/Al2O3. In a process of recycling the polyester fabric, the multifunctional catalyst simultaneously decolorizes and depolymerizes the polyester fabric. The first functional ionic liquid is used to decolorize the polyester fabric, and the second functional ionic liquid is used to depolymerize the polyester fabric.

Abstract: A transporting device can transport at least one product, the transporting device includes a mounting frame, a driving mechanism, a transmitting mechanism including a plurality of bent portions, a plurality of guiding mechanisms, and a supporting mechanism. Each guiding mechanism includes a rotating wheel and a guiding plate. Each bent portion is connected to the rotating wheel. The guiding plate is connected to the rotating wheel. The supporting mechanism can support the product. The driving mechanism is further connected to the rotating wheel and can drive the transmitting mechanism to rotate to drive the supporting mechanism to move. The driving mechanism is further connected to the guiding plate, the guiding plate and the rotating wheel can synchronously rotate to drive the supporting mechanism to pass through the bent portions. The present disclosure further provides a heating device.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.

Abstract: A circuit board cleaning system includes a cleaning tank, an ion exchange resin column, and a pump unit. The cleaning tank accommodates a cleaning liquid and allows a circuit board to be immersed in the cleaning liquid. The cleaning liquid includes a liquid water and a hydrocarbon-based surfactant. An ion exchange resin filled in the ion exchange resin column is a basic ion exchange resin. The pump unit is configured to pump the cleaning liquid into the ion exchange resin column, and enable the cleaning liquid to pass through the ion exchange resin column. When the cleaning liquid passes through the ion exchange resin column, the basic ion exchange resin deprotonates the hydrocarbon-based surfactant. After the cleaning liquid passes through the ion exchange resin column, the cleaning liquid is returned to the cleaning tank to remove acidic residue remaining on a surface of the circuit board.

Abstract: A method includes forming an optical engine, which includes a photonic die. The photonic die further includes a grating coupler. The method further includes forming a fiber unit including a fiber platform having a groove, and an optical fiber attached to the fiber platform. The optical fiber extends into the groove. The fiber platform further includes a reflector. The fiber unit is attached to the optical engine, and the reflector is configured to deflect a light beam, so that the light beam emitted by a first one of the optical fiber and the grating coupler is received by a second one of the optical fiber and the grating coupler.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: A navigation system includes: a communication unit configured to receive vehicle environment information of a user vehicle, the vehicle environment information including proximate vehicle information representing proximately located vehicles relative to the user vehicle; and a control unit, coupled to the communication unit, configured to: determine lane reference vehicles from the proximately located vehicles based on a vehicle type of the proximately located vehicles; monitor the relative location of the lane reference vehicles; generate a road lane model including a lane delineation estimation based on the relative location of the lane reference vehicles; and calculate a lane position of the user vehicle according to the lane delineation estimation based on a lateral position shift of the user vehicle.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.

Abstract: The present application provides a method of preparing lithium-friendly colloid paint. The method comprises functionalizing a carbon nanotube material to obtain a plurality of carbon nanotubes with functional groups; dispersing the of carbon nanotube material with functional groups in a solution containing nitrogen molecules to from the dispersion liquid to obtain a carbon nanotube precursor; heat-treating the carbon nanotube precursors to obtain a plurality of nitrogen-doped carbon nanotubes; dispersing the plurality of nitrogen-doped carbon nanotubes in an organic solvent, and adding a dispersant obtain a nitrogen-doped carbon nanotube solution precursor; and providing a polymer material colloid and a lithium salt, and uniformly mixing the nitrogen-doped carbon nanotube solution precursor, the lithium salt and the polymer material colloid.

Abstract: A power consumption monitoring device includes a sensor, a storage, and a processor. The sensor is configured to detect a power-consuming device quantity and a power consumption amount. The storage is configured to store the power-consuming device quantity and the power consumption amount. The processor is communicatively connected to the sensor and the storage. The processor is configured to calculate a power-consuming device idling indicator based on the power-consuming device quantity and the power consumption amount in a monitoring time interval, wherein the power-consuming device idling indicator is used for indicating a deviation status of the power-consuming device quantity and the power consumption amount. The processor is further configured to determine whether the power-consuming device idling indicator exceeds a warning threshold. In response to the power-consuming device idling indicator exceeding the warning threshold, the processor is further configured to generate a warning message.

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulant, and forming an interconnect structure over and electrically connecting to the first device die and the second device die. A waveguide is formed in the interconnect structure. An optical-engine based interconnect component is bonded to the interconnect structure. The optical-engine based interconnect component forms a part of a signal path that connects the first device die to the second device die.

Abstract: Embodiments of the disclosure provide for improved print position compensation, for example to improve accuracy of print job(s) performed by a printer. The print position compensation enables an offset of the time until printing occurs on a print media to account for changes and/or erroneous movement in a print media, such as due to slippage and/or other results of a force applied to the print media. Particular embodiments determine data values derived both for an output phase and a retraction phase of the printer's operation. Various embodiments generate a print position compensation based on sensor-based edge position distances determined during each of a media output phase and a media retraction phase. Alternatively or additionally various embodiments generate a print position compensation based on sensor-based media movement phase timestamp differentials determined during each of a media output phase and a media retraction phase.

Abstract: A processing element array includes N processing elements (PE) arranged linearly, N?2, and an operating method of the PE array includes: performing a first data transmission procedure, where an initial value of I is 1 and the first data transmission procedure includes: operating, by an ith PE, according to a first datum stored in itself, and sending the first datum to other PEs for their operations, adding 1 to I when I<N, and performing the first data transmission procedure again, performing a second data transmission procedure when I is equal to N, which includes: operating, by the Jth PE, according to a second datum stored in itself, and sending the second datum to other PEs for their operations, reducing J by 1 when J>1 and the (J?1)th PE has the second datum, and performing the second data transmission procedure again.