Patents by Inventor Wei Chao

Wei Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220362815
    Abstract: The present disclosure describes a wafer cleaning process in which a drained cleaning solution, which is used to remove metal contaminants from the wafer, is sampled and analyzed to determine the concentration of metal ions in the solution. The wafer cleaning process includes dispensing, in a wafer cleaning station, a chemical solution on one or more wafers; collecting the dispensed chemical solution; determining a concentration of contaminants in the chemical solution; in response to the concentration of the contaminants being greater than a baseline value, adjusting one or more parameters in the cleaning process; and in response to the concentration of the contaminants being equal to or less than the baseline value, transferring the one or more wafers out of the wafer cleaning station.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Chao, Shu-Yen Wang
  • Publication number: 20220359588
    Abstract: A method includes performing a first lithography process using a first pattern of a first photomask to form a first photoresist pattern on a front side of a device substrate; performing a first implantation process using the first pattern as a mask to form first isolation regions in the device substrate; after performing the first implantation process, performing a second lithography process using a second pattern of a second photomask to form a second photoresist pattern on the front side of the device substrate, the second pattern being shifted from the first pattern by a distance less than the first pitch and in the first direction; performing a second implantation process using the second photoresist pattern as a mask to form second isolation regions in the device substrate and spaced apart from the first isolation regions; and forming pixels between the first and second isolation regions.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao CHIU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20220359188
    Abstract: In an embodiment, a method includes: receiving a wafer from a first dilution tank; immersing the wafer in a deionization tank, wherein the deionization tank comprises a tank solution that comprises a deionizing solution; determining a metal ion concentration within the tank solution; performing remediation within the deionization tank in response to determining that the metal ion concentration is greater than a threshold value; and moving the wafer to a second dilution tank.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Inventors: Chih-Wei CHAO, Shu-Yen WANG
  • Publication number: 20220359726
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Po-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
  • Publication number: 20220352153
    Abstract: The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Wei Tseng, Jiun-Ming Kuo, Yuan-Ching Peng, Kuo-Yi Chao
  • Publication number: 20220344353
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
  • Publication number: 20220334880
    Abstract: A tensor accelerator includes two tile execution units and a bidirectional queue. Each of the tile execution units includes a buffer, a plurality of arithmetic logic units, a network, and a selector. The buffer includes a plurality of memory cells. The network is coupled to the plurality of memory cells. The selector is coupled to the network and the plurality of arithmetic logic units. The bidirectional queue is coupled between the selectors of the tile execution units.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Shao-Yi Chien, Yu-Sheng Lin, Wei-Chao Chen
  • Patent number: 11474484
    Abstract: A method for training a locomotion controller of a robotic animal comprising obtaining a motion data of a reference animal, an environmental parameter, and a disturbance parameter; generating a plurality of primitive distributions and a first primitive influence according to the motion data by a policy network; selecting a current state of the reference animal from the motion data and set an adapting state of the reference animal; generating a second primitive influence, by the policy network, according to the current state, the adapting state, and the plurality of primitive distributions at least; and training the policy network according to a result determined by a discriminator according to the first primitive influence and the second primitive influence.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 18, 2022
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Ying-Sheng Luo, Jonathan Hans Soeseno, Trista Pei-Chun Chen, Wei-Chao Chen
  • Patent number: 11461604
    Abstract: Embodiments of the disclosure provide for improved print position compensation, for example to improve accuracy of print job(s) performed by a printer. The print position compensation enables an offset of the time until printing occurs on a print media to account for changes and/or erroneous movement in a print media, such as due to slippage and/or other results of a force applied to the print media. Particular embodiments determine data values derived both for an output phase and a retraction phase of the printer's operation. Various embodiments generate a print position compensation based on sensor-based edge position distances determined during each of a media output phase and a media retraction phase. Alternatively or additionally various embodiments generate a print position compensation based on sensor-based media movement phase timestamp differentials determined during each of a media output phase and a media retraction phase.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 4, 2022
    Assignee: Datamax-O'Neil Corporation
    Inventors: Cheng Khoon Ng, Heng Yew Lim, Shufeng Zheng, Jang Wei Chao
  • Publication number: 20220308421
    Abstract: The present disclosure provides an optical element driving mechanism, which includes a movable part, a fixed assembly, and a driving assembly. The movable part is configured to be connected to an optical element. The fixed assembly has a first opening, and the movable part is movable relative to the fixed assembly along a first axis. The driving assembly is configured to drive the movable part to move between a first position and a second position relative to the fixed assembly, so that the optical element selectively overlaps the first opening.
    Type: Application
    Filed: March 29, 2022
    Publication date: September 29, 2022
    Inventors: Shih-Wei HUNG, Sheng-Zong CHEN, Ko-Lun CHAO
  • Publication number: 20220301943
    Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
  • Publication number: 20220302097
    Abstract: An LED device includes a substrate, a conductive layer, an LED chip, and a discharge element. The substrate has upper and lower surfaces and four edges interconnected to one another and surrounding the upper surface. The conductive layer is formed on the upper surface, and has first and second regions electrically separated by a trench. The trench has a first segment inclined relative to each edge of the substrate by a predetermined angle ranging between 0 and 90 degrees, and a second segment connected to the first segment. The LED chip is disposed across the first segment, and the discharge element is disposed across the second segment, both interconnecting the first and second regions.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 22, 2022
    Inventors: Shunyi CHEN, Junpeng SHI, Weng-Tack WONG, Chen-ke HSU, Chih-Wei CHAO
  • Patent number: 11444176
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
  • Publication number: 20220285155
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 8, 2022
    Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Yu-Wen CHEN, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20220285203
    Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 8, 2022
    Inventors: Wei-Chao CHIU, Yu-Wen CHEN, Yong-Jin LIOU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20220265058
    Abstract: Provided are an air cell device and an air mattress system thereof. The air cell device includes an air cell which has therein an upper connection segment and a lower connection segment. The upper connection segment and the lower connection segment each have a curved portion whereby the air cell is partitioned to become a multilayered air cell so as to mitigate air cell bending or air cell inversion, thereby improving the lying human being's comfort.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 25, 2022
    Inventors: CHIH-KUANG CHANG, SHENG-WEI LIN, CHIN-CHANG LIN, YUE-YIN CHAO, YU-HAO CHEN
  • Patent number: 11424364
    Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xi-Zong Chen, Te-Chih Hsiung, Cha-Hsin Chao, Yi-Wei Chiu
  • Patent number: 11416766
    Abstract: In an approach to detecting the transmission of messages, analyzing said messages, calculating a message risk score and transmitting a warning notification, one or more computer processors detect transmission of a message from a user to a selected recipient. The one or more computer processors extract message information from the detected message. The one or more computer processors retrieve one or more historical conversations between the user and the selected recipient of the detected message. The one or more computer processors determine a risk score corresponding to sending the detected message to the selected recipient based on applying the extracted message information and the retrieved historical conversations to a cognitive model.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: August 16, 2022
    Assignee: International Business Machines Corporation
    Inventors: Tzu-Chen Chao, Ching-Chun Liu, Ci-Wei Lan, Tao-Hung Jung, Yu-Siang Chen
  • Publication number: 20220251725
    Abstract: A method of growing on-axis silicon carbide single crystal includes the steps of (A) sieving a silicon carbide source material by size, and only the part that has a size larger than 1 cm is adopted for use as a sieved silicon carbide source material; (B) filling the sieved silicon carbide source material in the bottom of a graphite crucible; (C) positioning an on-axis silicon carbide on a top of the graphite crucible to serve as a seed crystal; (D) placing the graphite crucible having the sieved silicon carbide source material and the seed crystal received therein in an induction furnace for the physical vapor transport process; (E) starting a silicon carbide crystal growth process; and (F) obtaining a silicon carbide single crystal.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 11, 2022
    Inventors: CHIH-WEI KUO, CHENG-JUNG KO, HSUEH-I CHEN, JUN-BIN HUANG, YING-TSUNG CHAO, CHIA-HUNG TAI
  • Publication number: 20220254929
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer.
    Type: Application
    Filed: April 26, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao LIN, Wei-Sheng YUN, Tung-Ying LEE