Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.

Abstract: Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

Abstract: A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.

Abstract: A buried gate structure and a method for forming the same are provided. The structure includes first and second gate dielectric layers respectively formed on the surface of the lower portion and the surface of the upper portion of a gate trench of the semiconductor substrate. The structure includes a first gate electrode formed on the first gate dielectric layer. The structure includes an insulating cap layer formed on the first gate electrode to fill the remaining space of the gate trench. The first gate dielectric layer includes a negative capacitance dielectric material. The second gate dielectric layer includes a different dielectric material than the negative capacitance dielectric material. The interface between the first gate dielectric layer and the second gate dielectric layer is lower than the bottom surfaces of the source region and the drain region of the semiconductor substrate.

Abstract: An apparatus is disclosed for determining validity of a measured in-blood percentage of oxygenated hemoglobin. The apparatus has multiple pulse oximetry channels having at least three light sources of at least three distinct wavelengths, which are detected and converted to digital signals. The light sources are selectively activated, and two or more estimated in-blood percentages of oxygenated hemoglobin are calculated. It is determined whether a signal quality associated with the calculated in-blood percentages exceeds a predetermined accuracy threshold, and an associated validity indication is provided.

Abstract: System boot-up can be enabled in low temperature environments. A laptop or other battery-powered computing device can include multiple batteries and a battery architecture that allows the multiple batteries to simultaneously discharge to thereby provide adequate power to boot the system in low temperature environments. The battery architecture may also allow a battery with a higher relative state of charge to charge another battery with a lower relative state of charge to thereby equalize the batteries' relative states of charge.

Abstract: System boot-up can be enabled in low temperature environments. A laptop or other battery-powered computing device can include multiple batteries and a battery architecture that allows the multiple batteries to simultaneously discharge to thereby provide adequate power to boot the system in low temperature environments. The battery architecture may also allow a battery with a higher relative state of charge to charge another battery with a lower relative state of charge to thereby equalize the batteries' relative states of charge.

Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.

Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.

Abstract: A semiconductor structure includes a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, a source region and a drain region, a bit line contact, and a storage node contact. The trench is disposed in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on a top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer. The source region and the drain region are disposed in the substrate and disposed on opposite sides of the first conductive layer. The bit line contact is disposed on one of the source region and the drain region, and the storage node contact is disposed on the other of the source region and the drain region.

Abstract: A method and system for monitoring and controlling a semiconductor process are provided. The method includes: forming at least one active region on a substrate; forming a first patterned photoresist layer for defining at least two word lines on the active region after forming the active region; detecting and measuring positions and dimensions of the active region and the first patterned photoresist layer and calculating estimated areas of at least two estimated contact windows in the active region according to a predefined position of at least one bit line; adjusting the predefined position of the at least one bit line according to the estimated areas of the at least two estimated contact windows in the active region; and forming a second patterned photoresist layer on the substrate. The second patterned photoresist layer corresponds to the adjusted predefined position of the at least one bit line.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.

Abstract: A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.

Abstract: A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.

Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.

Abstract: An apparatus is disclosed for determining validity of a measured in-blood percentage of oxygenated hemoglobin. The apparatus has multiple pulse oximetry channels having at least three light sources of at least three distinct wavelengths, which are detected and converted to digital signals. The light sources are selectively activated, and two or more estimated in-blood percentages of oxygenated hemoglobin are calculated. It is determined whether a signal quality associated with the calculated in-blood percentages exceeds a predetermined accuracy threshold, and an associated validity indication is provided.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.