Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and landing pads. The substrate has an array area and a peripheral area, and the landing pads are disposed on the substrate and in the array area. The semiconductor structure also includes conductive pillars disposed on the landing pads and a bottom support layer disposed between the bottoms of the conductive pillars. The semiconductor structure further includes a protective layer disposed on the bottom support layer and an additional support layer disposed on the protective layer. Moreover, the semiconductor structure includes a central support layer disposed above the additional support layer and a top support layer disposed above the central support layer. The additional support layer, the central support layer, and the top support layer are all disposed between the conductive pillars.

Abstract: Providing are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a first isolation structure, a second isolation structure, a word line, a pad layer, a cover layer and a dummy pattern. The substrate has a memory device region and a peripheral region. The first isolation structure is disposed in the substrate in the memory device region to define an active area. The second isolation structure is disposed in the substrate in the peripheral region. The word line is disposed in the substrate in the active area. The pad layer is disposed on the substrate in the memory device region. The cover layer is disposed on the pad layer and extends downward to the top surface of the word line. The dummy pattern is disposed in the second isolation structure.

Abstract: Provided are a detection system, compensation method and computer-readable recording medium applicable to semiconductor surface morphology to provide feature information corresponding to spectral signals to a neural network model and provide feature information corresponding to spectral signals, a detected height, and an actual height actually measured to another neural network model. The combinational neural network models thus trained and built can generate a compensation value for a to-correct height corresponding to a to-correct spectral signal having variability. The compensation value provides required compensation for height information to not only enhance the precision of the detection of semiconductor surface morphology but also enhance the reliability of the detection system.

Abstract: A three-dimensional semiconductor device includes a stack of alternating memory cell layers and insulating layers over a substrate, and several bit lines formed on the substrate and separated from each other. The bit lines and the memory cell layers define an array of stacked memory cells that includes several memory cells. One of the memory cells includes a body, a gate structure and a conductive portion. The body that is on the substrate has a first surface and a second surface opposite the first surface. One side of the body is connected to one of the bit lines. The gate structure and the conductive portion are formed on the opposite first and second surfaces. The conductive portion is formed between adjacent memory cell layers and is in direct contact with the body.

Abstract: Provided is a flash memory device including a gate stack structure, at least three channel pillars, a charge storage structure, at least three source line, and at least three bit lines. The gate stack structure is disposed above a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately each other. The at least three channel pillars extend through the gate stack structure. The at least three channel pillars are electrically isolated from one another. The charge storage structure is disposed between the plurality of gate layers and the at least three channel pillars. The at least three source line are disposed below the gate stack structure and electrically connected to the at least three channel pillars. The at least three bit lines are disposed above the gate stack structure, and electrically connected to the at least three channel pillars.

Abstract: A DRAM device includes a substrate, bit lines, node contact plugs, dummy bit lines, a dummy insulating structure, and a cap layer. The substrate includes an array region, a peripheral region and a dummy region between the array region and the peripheral region. The bit lines are over the substrate and in the array region. The node contact plugs are in the array region. Each of the node contact plugs is on the substrate at one side of a corresponding one of the bit lines. The dummy bit lines are over the substrate and in the dummy region. The dummy insulating structure is between the dummy bit lines. The dummy insulating structure is arranged along with the node contact plugs. The cap layer is outside the array region to cover top portions of the dummy bit lines and top portion of the dummy insulating structure.

Abstract: A memory device includes a substrate, word line structures, bit line structures, dummy bit line structures, partition walls, and conductive plugs. The bit line structures are disposed above the substrate and extend from the array region to a transition region in the substrate. The dummy bit line structures are disposed in the transition region in the substrate, adjacent to the bit line structures, and extending along the second direction. The partition walls are disposed above the bit line structures and the dummy bit line structures, extending along the first direction. The conductive plugs are located in the transition region in the substrate. Each of the conductive plugs is located between two adjacent ones of the dummy bit line structures, and extends through the partition walls, and is electrically connected to one of the word line structures.

Abstract: A method and system for monitoring and controlling a semiconductor process are provided. The method includes: forming at least one active region on a substrate; forming a first patterned photoresist layer for defining at least two word lines on the active region after forming the active region; detecting and measuring positions and dimensions of the active region and the first patterned photoresist layer and calculating estimated areas of at least two estimated contact windows in the active region according to a predefined position of at least one bit line; adjusting the predefined position of the at least one bit line according to the estimated areas of the at least two estimated contact windows in the active region; and forming a second patterned photoresist layer on the substrate. The second patterned photoresist layer corresponds to the adjusted predefined position of the at least one bit line.

Abstract: A method for forming a semiconductor structure is provided. The formation method includes forming a trench in a substrate. A first conductive layer is formed in the trench. A second conductive layer is formed on the first conductive layer. A sacrificial layer is formed on the second conductive layer. The sacrificial layer is partially removed. The second conductive layer is etched with the remaining portion of the sacrificial layer as an etching mask to expose a portion of the second conductive layer. A third conductive layer is formed on the second conductive layer, wherein the third conductive layer covers the exposed portion of the second conductive layer.

Abstract: Provided are a detection system, compensation method and computer-readable recording medium applicable to semiconductor surface morphology to provide feature information corresponding to spectral signals to a neural network model and provide feature information corresponding to spectral signals, a detected height, and an actual height actually measured to another neural network model. The combinational neural network models thus trained and built can generate a compensation value for a to-correct height corresponding to a to-correct spectral signal having variability. The compensation value provides required compensation for height information to not only enhance the precision of the detection of semiconductor surface morphology but also enhance the reliability of the detection system.

Abstract: A semiconductor structure includes a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, a source region and a drain region, a bit line contact, and a storage node contact. The trench is disposed in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on a top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer. The source region and the drain region are disposed in the substrate and disposed on opposite sides of the first conductive layer. The bit line contact is disposed on one of the source region and the drain region, and the storage node contact is disposed on the other of the source region and the drain region.

Abstract: A method for forming a semiconductor structure includes the following steps. A first trench is formed in a semiconductor substrate, and a first nitride layer is formed along a sidewall and a bottom surface of the first trench. A first oxide layer is formed over the first nitride layer to fill the first trench, and the first oxide layer is recessed from the first trench to form a first recess. A portion of the first nitride layer exposed from the first recess is etched, and a second nitride layer is formed along a sidewall and a bottom surface of the first recess. The second nitride layer includes a first portion along the bottom surface and a second portion along the sidewall. The second portion is removed, and a second oxide layer is formed over the first portion to fill the first recess.

Abstract: This disclosure provides systems, methods, and devices for wireless communication that support transmission of power limit indications for a UE associated with different frequency bands. In a first aspect, a method of wireless communication includes detecting a first trigger condition for transmission of at least a first indication of a first transmission power limit of the UE and a second indication of a second transmission power limit of the UE, wherein the first transmission power limit is associated with a first frequency band supported by the UE and the second transmission power limit is associated with a second frequency band supported by the UE and transmitting, to a first network node associated with the first frequency band, the first indication and the second indication in accordance with detection of the first trigger condition. Other aspects and features are also claimed and described.

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.

Abstract: A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.

Abstract: Provided is a flash memory device including a gate stack structure, at least three channel pillars, a charge storage structure, at least three source line, and at least three bit lines. The gate stack structure is disposed above a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately each other. The at least three channel pillars extend through the gate stack structure. The at least three channel pillars are electrically isolated from one another. The charge storage structure is disposed between the plurality of gate layers and the at least three channel pillars. The at least three source line are disposed below the gate stack structure and electrically connected to the at least three channel pillars. The at least three bit lines are disposed above the gate stack structure, and electrically connected to the at least three channel pillars.

Abstract: A buried gate structure and a method for forming the same are provided. The structure includes first and second gate dielectric layers respectively formed on the surface of the lower portion and the surface of the upper portion of a gate trench of the semiconductor substrate. The structure includes a first gate electrode formed on the first gate dielectric layer. The structure includes an insulating cap layer formed on the first gate electrode to fill the remaining space of the gate trench. The first gate dielectric layer includes a negative capacitance dielectric material. The second gate dielectric layer includes a different dielectric material than the negative capacitance dielectric material. The interface between the first gate dielectric layer and the second gate dielectric layer is lower than the bottom surfaces of the source region and the drain region of the semiconductor substrate.

Abstract: An apparatus is disclosed for determining validity of a measured in-blood percentage of oxygenated hemoglobin. The apparatus has multiple pulse oximetry channels having at least three light sources of at least three distinct wavelengths, which are detected and converted to digital signals. The light sources are selectively activated, and two or more estimated in-blood percentages of oxygenated hemoglobin are calculated. It is determined whether a signal quality associated with the calculated in-blood percentages exceeds a predetermined accuracy threshold, and an associated validity indication is provided.

Abstract: System boot-up can be enabled in low temperature environments. A laptop or other battery-powered computing device can include multiple batteries and a battery architecture that allows the multiple batteries to simultaneously discharge to thereby provide adequate power to boot the system in low temperature environments. The battery architecture may also allow a battery with a higher relative state of charge to charge another battery with a lower relative state of charge to thereby equalize the batteries' relative states of charge.