Patents by Inventor Wei-Che Chang

Wei-Che Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111177
    Abstract: A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Ying-Chu YEN, Wei-Che CHANG
  • Patent number: 10910384
    Abstract: A method of fabricating a memory device includes firming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: February 2, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Ying-Chu Yen, Wei-Che Chang
  • Patent number: 10910380
    Abstract: A method of manufacturing a DRAM includes isolation structures and word line sets are formed in the substrate. A conductive material is formed on the substrate. Conductive material is removed to form first openings in the conductive material. The first openings expose surfaces of the substrate in the first areas and divide the conductive material into conductive layers, thereby the conductive layers are located on surfaces of the substrate in the second areas. A first dielectric material is filled in the first openings so as to form first dielectric layers on the substrate in the first areas. Top surfaces of the conductive layers are lower than top surfaces of the first dielectric layers. Second dielectric layers are formed respectively in the conductive layers. Capacitors are formed respectively on the conductive posts.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Huang-Nan Chen, Wei-Che Chang
  • Publication number: 20210013211
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Wei-Che CHANG, Tzu-Ming OU YANG
  • Patent number: 10797057
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Winbond Electronic Corp.
    Inventors: Wei-Che Chang, Tzu-Ming Ou Yang
  • Publication number: 20200119020
    Abstract: A method of manufacturing a DRAM includes isolation structures and word line sets are formed in the substrate. A conductive material is formed on the substrate. Conductive material is removed to form first openings in the conductive material. The first openings expose surfaces of the substrate in the first areas and divide the conductive material into conductive layers, thereby the conductive layers are located on surfaces of the substrate in the second areas. A first dielectric material is filled in the first openings so as to form first dielectric layers on the substrate in the first areas. Top surfaces of the conductive layers are lower than top surfaces of the first dielectric layers. Second dielectric layers are formed respectively in the conductive layers. Capacitors are formed respectively on the conductive posts.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 16, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Huang-Nan Chen, Wei-Che Chang
  • Publication number: 20190393226
    Abstract: A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line.
    Type: Application
    Filed: November 21, 2018
    Publication date: December 26, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Yoshinori Tanaka, Wei-Che Chang, Kai Jen
  • Publication number: 20190348420
    Abstract: A method of fabricating a memory device includes firming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 14, 2019
    Inventors: Ying-Chu YEN, Wei-Che CHANG
  • Publication number: 20190312037
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.
    Type: Application
    Filed: November 7, 2018
    Publication date: October 10, 2019
    Inventors: Wei-Che CHANG, Tzu-Ming OU YANG
  • Patent number: 10424586
    Abstract: A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 24, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Ying-Chu Yen, Wei-Che Chang, Yoshinori Tanaka
  • Patent number: 10403573
    Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Wei-Che Chang
  • Patent number: 10366995
    Abstract: A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which are disposed in the substrate. The buried word line intersects the first isolation structures. The second isolation structure intersects the first isolation structures. A material of at least a portion of the second isolation structure is different from a material of the first isolation structures.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 30, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Wei-Che Chang, Yoshinori Tanaka
  • Patent number: 10332572
    Abstract: Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 25, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Wei-Che Chang, Yoshinori Tanaka
  • Publication number: 20190019542
    Abstract: Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions.
    Type: Application
    Filed: June 12, 2018
    Publication date: January 17, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Wei-Che Chang, Yoshinori Tanaka
  • Publication number: 20190019795
    Abstract: A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divide the substrate into active areas. The active areas are configured in the shape of band and arranged in an array. The word line sets are disposed in parallel in a Y direction in the substrate. The bit-line structures are disposed in parallel in an X direction on the substrate and cross the word line sets. The spacers are disposed in parallel in the X direction on sidewalls of the substrate, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminals of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active areas.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 17, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Huang-Nan Chen, Wei-Che Chang
  • Publication number: 20190006369
    Abstract: A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which are disposed in the substrate. The buried word line intersects the first isolation structures. The second isolation structure intersects the first isolation structures. A material of at least a portion of the second isolation structure is different from a material of the first isolation structures.
    Type: Application
    Filed: May 15, 2018
    Publication date: January 3, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Wei-Che Chang, Yoshinori Tanaka
  • Publication number: 20180358362
    Abstract: A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.
    Type: Application
    Filed: January 10, 2018
    Publication date: December 13, 2018
    Inventors: Ying-Chu YEN, Wei-Che CHANG, Yoshinori TANAKA
  • Patent number: 10083906
    Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes a semiconductor substrate having a trench, an oxide layer formed on a surface of the trench, and a buried word line formed in the trench having the oxide layer formed thereon. The oxide layer includes a first portion extending downward from a top surface of the semiconductor substrate, a second portion extending upward from a bottom portion of the trench, and a third portion formed between and adjoining the first portion and the second portion. The third portion tapers toward the second portion. The first portion of the oxide layer is located between the buried word line and the surface of the trench.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 25, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Kai Jen, Wei-Che Chang, Kazutaka Manabe, Kazuaki Takesako, Noriaki Ikeda, Yoshinori Tanaka
  • Patent number: 10074654
    Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: September 11, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe, Noriaki Ikeda, Wei-Che Chang
  • Publication number: 20180158774
    Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.
    Type: Application
    Filed: January 10, 2018
    Publication date: June 7, 2018
    Inventor: Wei-Che Chang