Abstract: A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.

Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes a semiconductor substrate having a trench, an oxide layer formed on a surface of the trench, and a buried word line formed in the trench having the oxide layer formed thereon. The oxide layer includes a first portion extending downward from a top surface of the semiconductor substrate, a second portion extending upward from a bottom portion of the trench, and a third portion formed between and adjoining the first portion and the second portion. The third portion tapers toward the second portion. The first portion of the oxide layer is located between the buried word line and the surface of the trench.

Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.

Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.

Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; forming a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

Abstract: A wearable electronic device including a first main body, a second main body, a wire, a first magnetic component and a second magnetic component is provided. The two ends of the wire are respectively connected to the first main body and the second main body. The first magnetic component is disposed on the first main body, and the second magnetic component is disposed on the second main body. The first magnetic component and the second magnetic component are attracted to each other along a direction parallel to an axis, so as to form a receiving structure. The first main body and the second main body rotate in relative to each other along the axis, so as to furl the wire into the receiving structure, and at least one of the first main body and the second main body includes an electronic component.

Abstract: A method of fabricating a memory device includes providing a substrate having a first region and a second region. A first dielectric layer is formed on the substrate in the first region. A conductive layer is formed on the substrate in the second region. A top surface of the conductive layer is lower than a top surface of the first dielectric layer. A second dielectric layer is formed on the substrate. A portion of the second dielectric layer and a portion of the conductive layer are removed to form a first opening in the conductive layer and the second dielectric layer in the second region. The first opening exposes a surface of the substrate. A portion of the substrate in the second region is removed to form a trench in the substrate in the second region. A third dielectric layer is formed in the trench and the first opening.

Abstract: A method and apparatus are disclosed for improving downlink control information in a wireless communication system. In one embodiment, the method includes receiving a first control signaling indicating a first transmission to a first UE, wherein the first control signaling is identified by a first identification used by the first UE. The method also includes receiving a second control signaling indicating a second transmission to a second UE, wherein the second control signaling is identified by a second identification used by the second UE. The method further includes decoding the first transmission based on information provided by at least the first control signaling and the second control signaling, wherein radio resource used by the first transmission is indicated by the second control signaling but is not indicated by the first control signaling.

Abstract: A method and apparatus are disclosed for implementing D2D service power control in a wireless communication system. The method includes the UE being served by an eNB. The method also includes computing a power information of a first channel transmission based on a power information of a first channel transmission included in a previous subframe and a first power offset associated with the first channel transmission. The method further includes transmitting a second channel transmission in subframe n where the power information of the second channel transmission is computed based on a power information of the first channel transmission in subframe n-1 and a second power offset associated with the second channel transmission.

Abstract: A method and apparatus are disclosed for supporting D2D (Device-to-Device) communication in a wireless communication system, wherein a first user equipment (UE) and a second user equipment are capable of D2D communication and are served by an evolved Node B (eNB). The method includes the second UE transmitting a first Scheduling Assignment (SA) and a first data to the first UE. The method also includes the second UE receiving a Hybrid Automatic Repeat Request Acknowledgement (HARQ-ACK) and a D2D power control information from first UE. The method further includes the second UE transmits a second SA and a second data to the first UE, wherein the second UE adjusts a transmission power of the second SA and the second data based on the D2D power control information received from the first UE.

Abstract: A method and apparatus are disclosed for supporting D2D (Device-to-Device) services in a wireless communication system, wherein a first user equipment (UE) and a second user equipment are capable of D2D communication and are served by an evolved Node B (eNB). The method includes the first UE transmitting a SA (Scheduling Assignment) and a data to the second UE. The method also includes the first UE transmitting a D2D power control information to the second UE.

Abstract: Methods and apparatuses for supporting device to device (D2D) communication are disclosed herein. One method includes monitoring, by a first UE, a scheduling assignment (SA) resource pool. The method also includes transmitting, by the first UE, a first SA in a first SA resource. The method further includes finding, by the first UE, unused SA resources in the SA resource pool. The method also includes transmitting, by the first UE, an extra SA in a second SA resource, wherein the second SA resource is within the unused SA resources.

Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; forming a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.

Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.

Abstract: A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.

Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.

Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.

Abstract: A method and a system for managing controllers suitable for searching and managing controllers of a plurality of servers on a network segment are provided. One of the servers is taken as a searching engine, and an account and a password of each controller is set therein. The searching engine is used for searching the controllers in the network segment, and using the account and the password of each of the controllers to login the controller for obtaining server information of the server where the controller is belonged. Accordingly, when a searching instruction is received from a client apparatus by the searching engine, the server information of the servers assigned by the searching instruction is provided to the client apparatus.