Patents by Inventor Wei-Che Hsieh

Wei-Che Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069431
    Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.
    Type: Application
    Filed: February 16, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Che HSIEH, Chien-Cheng Chen, Ping-Hsun Lin, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 11859242
    Abstract: Described herein are genetic recognition reagents comprising terminal aromatic moieties that bind specifically to a template nucleic acid and concatenate. Also provided are methods of using the genetic recognition reagents, e.g., to treat or diagnose a repeat expansion disorder, such as DMI.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 2, 2024
    Assignee: Carnegie Mellon University
    Inventors: Danith H. Ly, Wei-Che Hsieh, Raman Bahal
  • Publication number: 20230386826
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Patent number: 11830727
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Publication number: 20230282731
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Inventors: Wei-Che Hsieh, Chunyao Wang
  • Publication number: 20230205072
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.
    Type: Application
    Filed: February 27, 2023
    Publication date: June 29, 2023
    Inventors: Hung-Yi TSAI, Wei-Che HSIEH, Ta-Cheng LIEN, Hsin-Chang LEE, Ping-Hsun LIN, Hao-Ping CHENG, Ming-Wei CHEN, Szu-Ping TSAI
  • Publication number: 20230161240
    Abstract: In a method of manufacturing a reflective mask, an adhesion layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an absorber layer disposed over the capping layer, and a hard mask layer disposed over the absorber layer. A photoresist pattern is formed over the adhesion layer, the adhesion layer is patterned, the hard mask layer is patterned, and the absorber layer is patterned using the patterned hard mask layer as an etching mask. The photoresist layer has a higher adhesiveness to the adhesion layer than to the hard mask layer.
    Type: Application
    Filed: May 4, 2022
    Publication date: May 25, 2023
    Inventors: Wei-Che HSIEH, Chia-Ching CHU, Ya-Lun CHEN, Yu-Chung SU, Tzu-Yi WANG, Yahru CHENG, Ta-Cheng LIEN, Hsin-Chang LEE, Ching-Yu CHANG
  • Patent number: 11652158
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Che Hsieh, Chunyao Wang
  • Publication number: 20230087992
    Abstract: Photosensitive polymers and their use in photoresists for photolithographic processes are disclosed. The polymers are copolymers, with at least one monomer that includes pendant polycyclic aromatic groups and a second monomer that includes an acidic leaving group (ALG). The polymers have high resistance to etching and high development contrast.
    Type: Application
    Filed: March 15, 2022
    Publication date: March 23, 2023
    Inventors: Wei-Che Hsieh, Yu-Chung Su, Chia-Ching Chu, Tzu-Yi Wang, Ta-Cheng Lien, Hsin-Chang Lee, Ching-Yu Chang, Yahru Cheng
  • Patent number: 11592737
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Yi Tsai, Wei-Che Hsieh, Ta-Cheng Lien, Hsin-Chang Lee, Ping-Hsun Lin, Hao-Ping Cheng, Ming-Wei Chen, Szu-Ping Tsai
  • Publication number: 20230032950
    Abstract: A reflective mask includes a substrate, a lower reflective multilayer disposed over the substrate, an intermediate layer disposed over the lower reflective multilayer, an upper reflective multilayer disposed over the intermediate layer, a capping layer disposed over the upper reflective multilayer, and an absorber layer disposed in a trench formed in the upper reflective layers and over the intermediate layer. The intermediate layer includes a metal other than Cr, Ru, Si, Si compound and carbon.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Wei-Che HSIEH, Chi-Lun LU, Ping-Hsun LIN, Fu-Sheng CHU, Ta-Cheng LIEN, Hsin-Chang LEE
  • Publication number: 20220336202
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Publication number: 20220336628
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Wei-Che Hsieh, Chunyao Wang
  • Patent number: 11393674
    Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
  • Patent number: 11380776
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Che Hsieh, Chunyao Wang
  • Publication number: 20220102527
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.
    Type: Application
    Filed: February 16, 2021
    Publication date: March 31, 2022
    Inventors: Wei-Che Hsieh, Chunyao Wang
  • Publication number: 20210373430
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.
    Type: Application
    Filed: November 24, 2020
    Publication date: December 2, 2021
    Inventors: Hung-Yi TSAI, Wei-Che HSIEH, Ta-Cheng LIEN, Hsin-Chang LEE, Ping-Hsun LIN, Hao-Ping CHENG, Ming-Wei CHEN, Szu-Ping TSAI
  • Publication number: 20210333717
    Abstract: A method of fabricating a mask is provided. The method includes providing a hard mask layer disposed on top of absorber, a capping layer, and a multilayer that are disposed on a substrate. The method includes forming a middle layer over the hard mask layer, forming a photo resist layer over the middle layer, patterning the photo resist layer, etching the middle layer through the patterned photo resist layer, etching the hard mask layer through the patterned middle layer, and etching the absorber through the patterned hard mask layer. In some embodiments, etching the hard mask layer through the patterned middle layer includes a dry-etching process that has a first removal rate of the hard mask layer and a second removal rate of the middle layer, and a ratio of the first removal rate of the hard mask layer to the second removal rate of the middle layer is greater than 5.
    Type: Application
    Filed: October 30, 2020
    Publication date: October 28, 2021
    Inventors: Wei-Che HSIEH, Tzu-Yi WANG, Ping-Hsun LIN, Ta-Cheng LIEN, Hsin-Chang LEE, Huan-Ling LEE
  • Publication number: 20210230680
    Abstract: Described herein are divalent nucleobases that each binds two nucleic acid strands, matched or mismatched when incorporated into a nucleic acid or nucleic acid analog backbone, such as in a ?-peptide nucleic acid (?PNA). Also provided are genetic recognition reagents comprising one or more of the divalent nucleobases and a nucleic acid or nucleic acid analog backbone, such as a ?PNA backbone. Uses for the divalent nucleobases and monomers and genetic recognition reagents containing the divalent nucleobases also are provided.
    Type: Application
    Filed: June 7, 2019
    Publication date: July 29, 2021
    Inventors: Danith H. Ly, Shivaji A. Thadke, Ashif Y. Shaikh, Wei-Che Hsieh, Ali Nakhi, J. Dinithi Perera
  • Patent number: 10851407
    Abstract: A method of making optically pure preparations of chiral ?PNA (gamma peptide nucleic acid) monomers is provided. Nano structures comprising chiral ?PNA structures also are provided. Methods of amplifying and detecting specific nucleic acids, including in situ methods are provided as well as compositions and kits useful in those methods. Lastly, methods of converting nucleobase sequences from right-handed helical PNA, nucleic acid and nucleic acid analog structures to left-handed ?PNA, and vice-versa, are provided.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: December 1, 2020
    Assignee: Carnegie Mellon University
    Inventors: Danith H. Ly, Wei-Che Hsieh, Iulia Sacui, Arunava Manna