Patents by Inventor Wei-Che Hsieh
Wei-Che Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240069431Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.Type: ApplicationFiled: February 16, 2023Publication date: February 29, 2024Inventors: Wei-Che HSIEH, Chien-Cheng Chen, Ping-Hsun Lin, Ta-Cheng Lien, Hsin-Chang Lee
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Patent number: 11859242Abstract: Described herein are genetic recognition reagents comprising terminal aromatic moieties that bind specifically to a template nucleic acid and concatenate. Also provided are methods of using the genetic recognition reagents, e.g., to treat or diagnose a repeat expansion disorder, such as DMI.Type: GrantFiled: December 21, 2018Date of Patent: January 2, 2024Assignee: Carnegie Mellon UniversityInventors: Danith H. Ly, Wei-Che Hsieh, Raman Bahal
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Publication number: 20230386826Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: ApplicationFiled: July 25, 2023Publication date: November 30, 2023Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Patent number: 11830727Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: GrantFiled: June 30, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Publication number: 20230282731Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Inventors: Wei-Che Hsieh, Chunyao Wang
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Publication number: 20230205072Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Inventors: Hung-Yi TSAI, Wei-Che HSIEH, Ta-Cheng LIEN, Hsin-Chang LEE, Ping-Hsun LIN, Hao-Ping CHENG, Ming-Wei CHEN, Szu-Ping TSAI
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Publication number: 20230161240Abstract: In a method of manufacturing a reflective mask, an adhesion layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an absorber layer disposed over the capping layer, and a hard mask layer disposed over the absorber layer. A photoresist pattern is formed over the adhesion layer, the adhesion layer is patterned, the hard mask layer is patterned, and the absorber layer is patterned using the patterned hard mask layer as an etching mask. The photoresist layer has a higher adhesiveness to the adhesion layer than to the hard mask layer.Type: ApplicationFiled: May 4, 2022Publication date: May 25, 2023Inventors: Wei-Che HSIEH, Chia-Ching CHU, Ya-Lun CHEN, Yu-Chung SU, Tzu-Yi WANG, Yahru CHENG, Ta-Cheng LIEN, Hsin-Chang LEE, Ching-Yu CHANG
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Patent number: 11652158Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.Type: GrantFiled: June 30, 2022Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Che Hsieh, Chunyao Wang
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Publication number: 20230087992Abstract: Photosensitive polymers and their use in photoresists for photolithographic processes are disclosed. The polymers are copolymers, with at least one monomer that includes pendant polycyclic aromatic groups and a second monomer that includes an acidic leaving group (ALG). The polymers have high resistance to etching and high development contrast.Type: ApplicationFiled: March 15, 2022Publication date: March 23, 2023Inventors: Wei-Che Hsieh, Yu-Chung Su, Chia-Ching Chu, Tzu-Yi Wang, Ta-Cheng Lien, Hsin-Chang Lee, Ching-Yu Chang, Yahru Cheng
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Patent number: 11592737Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.Type: GrantFiled: November 24, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Yi Tsai, Wei-Che Hsieh, Ta-Cheng Lien, Hsin-Chang Lee, Ping-Hsun Lin, Hao-Ping Cheng, Ming-Wei Chen, Szu-Ping Tsai
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Publication number: 20230032950Abstract: A reflective mask includes a substrate, a lower reflective multilayer disposed over the substrate, an intermediate layer disposed over the lower reflective multilayer, an upper reflective multilayer disposed over the intermediate layer, a capping layer disposed over the upper reflective multilayer, and an absorber layer disposed in a trench formed in the upper reflective layers and over the intermediate layer. The intermediate layer includes a metal other than Cr, Ru, Si, Si compound and carbon.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Wei-Che HSIEH, Chi-Lun LU, Ping-Hsun LIN, Fu-Sheng CHU, Ta-Cheng LIEN, Hsin-Chang LEE
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Publication number: 20220336202Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Publication number: 20220336628Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Wei-Che Hsieh, Chunyao Wang
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Patent number: 11393674Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.Type: GrantFiled: May 18, 2018Date of Patent: July 19, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Che Hsieh, Ching Yu Huang, Hsin-Hao Yeh, Chunyao Wang, Tze-Liang Lee
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Patent number: 11380776Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.Type: GrantFiled: February 16, 2021Date of Patent: July 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Che Hsieh, Chunyao Wang
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Publication number: 20220102527Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.Type: ApplicationFiled: February 16, 2021Publication date: March 31, 2022Inventors: Wei-Che Hsieh, Chunyao Wang
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Publication number: 20210373430Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.Type: ApplicationFiled: November 24, 2020Publication date: December 2, 2021Inventors: Hung-Yi TSAI, Wei-Che HSIEH, Ta-Cheng LIEN, Hsin-Chang LEE, Ping-Hsun LIN, Hao-Ping CHENG, Ming-Wei CHEN, Szu-Ping TSAI
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Publication number: 20210333717Abstract: A method of fabricating a mask is provided. The method includes providing a hard mask layer disposed on top of absorber, a capping layer, and a multilayer that are disposed on a substrate. The method includes forming a middle layer over the hard mask layer, forming a photo resist layer over the middle layer, patterning the photo resist layer, etching the middle layer through the patterned photo resist layer, etching the hard mask layer through the patterned middle layer, and etching the absorber through the patterned hard mask layer. In some embodiments, etching the hard mask layer through the patterned middle layer includes a dry-etching process that has a first removal rate of the hard mask layer and a second removal rate of the middle layer, and a ratio of the first removal rate of the hard mask layer to the second removal rate of the middle layer is greater than 5.Type: ApplicationFiled: October 30, 2020Publication date: October 28, 2021Inventors: Wei-Che HSIEH, Tzu-Yi WANG, Ping-Hsun LIN, Ta-Cheng LIEN, Hsin-Chang LEE, Huan-Ling LEE
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Publication number: 20210230680Abstract: Described herein are divalent nucleobases that each binds two nucleic acid strands, matched or mismatched when incorporated into a nucleic acid or nucleic acid analog backbone, such as in a ?-peptide nucleic acid (?PNA). Also provided are genetic recognition reagents comprising one or more of the divalent nucleobases and a nucleic acid or nucleic acid analog backbone, such as a ?PNA backbone. Uses for the divalent nucleobases and monomers and genetic recognition reagents containing the divalent nucleobases also are provided.Type: ApplicationFiled: June 7, 2019Publication date: July 29, 2021Inventors: Danith H. Ly, Shivaji A. Thadke, Ashif Y. Shaikh, Wei-Che Hsieh, Ali Nakhi, J. Dinithi Perera
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Patent number: 10851407Abstract: A method of making optically pure preparations of chiral ?PNA (gamma peptide nucleic acid) monomers is provided. Nano structures comprising chiral ?PNA structures also are provided. Methods of amplifying and detecting specific nucleic acids, including in situ methods are provided as well as compositions and kits useful in those methods. Lastly, methods of converting nucleobase sequences from right-handed helical PNA, nucleic acid and nucleic acid analog structures to left-handed ?PNA, and vice-versa, are provided.Type: GrantFiled: May 8, 2015Date of Patent: December 1, 2020Assignee: Carnegie Mellon UniversityInventors: Danith H. Ly, Wei-Che Hsieh, Iulia Sacui, Arunava Manna