Abstract: A three-dimensional flash memory device may be a AND flash memory device. The three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of conductive pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.

Abstract: A head-mounted display device and a control method for an eye-tracking operation are provided. The head-mounted display device includes a frame, a track, a sensor and a controller. The track is disposed on a peripheral region of the frame. The sensor is disposed on the track, and is configured to capture a target image of a target area. The controller is coupled to the sensor, is configured to generate a control signal according to the target image, and adjust a position of the sensor on the peripheral region by moving the sensor according to the control signal.

Abstract: A memory structure includes a substrate; a first gate structure, a second gate structure and a third gate structure disposed on the substrate, separated from each other along the first direction and respectively extending along the second direction and the third direction; channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along the first direction; dielectric films disposed between the first gate structure, the second gate structure, the third gate structure and the channel bodies; and a first side plug electrically connected to the substrate and the channel bodies. The first gate structure, the second gate structure and the third gate structure surround each of the dielectric films and each of the channel bodies, and the dielectric films do not include a charge storage structure.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for sidebar communication threads forked from, or related to, a principal thread. Messages in the sidebar communication thread may include a history of the principal thread, including one or more messages from the principal thread, and may include a proposed principal thread message that is the subject of the sidebar thread discussion. The sidebar thread may also include sidebar thread messages that carries the conversation of the sidebar thread participants. Once a termination condition is reached for the sidebar thread, the sidebar thread terminates and either the proposed principal thread message (as potentially modified by participants of the sidebar thread) becomes an accepted principal thread message and it is posted to the principal thread as if it was sent by the sidebar initiator or no message is posted (e.g., the proposed principal thread message is rejected).

Abstract: A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for sidebar communication threads forked from, or related to, a principal thread. Messages in the sidebar communication thread may include a history of the principal thread, including one or more messages from the principal thread, and may include a proposed principal thread message that is the subject of the sidebar thread discussion. The sidebar thread may also include sidebar thread messages that carries the conversation of the sidebar thread participants. Once a termination condition is reached for the sidebar thread, the sidebar thread terminates and either the proposed principal thread message (as potentially modified by participants of the sidebar thread) becomes an accepted principal thread message and it is posted to the principal thread as if it was sent by the sidebar initiator or no message is posted (e.g., the proposed principal thread message is rejected).

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.

Abstract: Disclosed in some examples are display systems, methods, devices, and machine-readable mediums which provide for a gesture-based method for specifying a region of a display in which to show shared content. Also disclosed are pairing methods for associating the region of the display with a content source device, methods for sharing content within the region, and methods for providing input from the region back to the content source device. Also disclosed in some examples are display systems, methods, devices, and machine-readable mediums which provide for notification handling for user interfaces.

Abstract: A system provides permission controls for group messages. A system can support user accessibility by the use of a permissions that indicates that a user has accessibility needs with respect to a voice input. When a user is known to have accessibility issue with providing a voice input, a system data structure, such as a Teams directory, can indicate when specific users have special needs. The system can grant them with rights to prevent others from providing messages to a message thread. This allows that person to become a presenter of a meeting while using a message thread to give their presentation without interruption from others. The system can unlock the thread and allow others to provide messages when the user is done with their presentation. By controlling a message thread in this manner, a system can allow users having special needs to participate as a meeting presenter.

Abstract: A memory cell circuit, a memory cell array structure and a manufacturing method thereof are provided. The memory cell circuit includes a first transistor, a second transistor and a capacitor. The first transistor has a first end electrically coupled to a bit line, and a gate of the first transistor is electrically coupled to a primary word line. The second transistor has a first end electrically coupled to a second end of the first transistor, and a gate of the second transistor is electrically coupled to an auxiliary word line. A first end of the capacitor is electrically coupled to a second end of the second transistor and a second end of the capacitor receives a reference voltage.

Abstract: A memory device based on thyristors, comprises the following elements. A plurality of gate structures, are continuous structures in the first direction. A plurality of bit lines, extending in a second direction substantially perpendicular to the first direction. A plurality of source lines, extending in the first direction. A plurality of channels, extending in a third direction substantially perpendicular to the first direction and the second direction, and penetrating the gate structures. The first doped regions of the channels are coupled to the bit lines, and the second doped regions of the channels are coupled to the source lines. A plurality of memory units formed by the gate structures and corresponding channels. The source lines are arranged in sequence according to the second direction to form a stair structure, and the lengths of the source lines decrease in sequence in the first direction.

Abstract: A head-mounted display device includes a main body, a first sensor and a second sensor. The first sensor is disposed on a first setting area of the main body. The second sensor is disposed on a second setting area of the main body. The first setting area and the second setting area respectively have a first central point and a second central point, where the first central point and the second central point are disposed on a horizontal axis. There is a first angle between a connection line of the first central point and the first sensor with the horizontal axis, and there is a second angle between a connection line of the second central point and the second sensor with the horizontal axis, where the first angle is different from the second angle.

Abstract: Disclosed in some examples are methods, systems and machine-readable mediums which allow for more secure authentication attempts by implementing authentication systems with credentials that include interspersed noise symbols in positions determined by the user. These systems secure against eavesdroppers such as shoulder-surfers or man-in-the middle attacks as it is difficult for an eavesdropper to separate the noise symbols from legitimate credential symbols.

Abstract: An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.

Abstract: A sewing machine includes a main body and a quick release needle plate module. The main body includes a base seat having an inner frame, and an outer case that is mounted to the inner frame and that defines an accommodating compartment. The quick release needle plate module includes a catch member, and a needle plate that covers the accommodating compartment, that is detachably pivoted to a rear section of the inner frame, and that engages the catch member. The quick release needle plate module further includes a press member inserted through the outer case and the inner frame, and operable to push the catch member to disengage the catch member. The needle plate has a plate body that covers the accommodating compartment, and a resilient member mounted between the inner frame and the plate body for driving pivot action of the plate body away from the inner frame.

Abstract: A semiconductor circuit and an operating method for the same are provided. The semiconductor circuit includes strings. The strings include a first string and a second string. The first string includes a first device unit and a second device unit in series. The first string has a weight signal W1. The first device unit has an input signal A. The second device unit has an input signal B. The second string includes a third device unit and a fourth device unit in series. The second string has a weight signal W2. The third device unit has an input signal ?. The fourth device unit has an input signal B. An output signal of the semiconductor circuit is a sum of output string signals of the strings.

Abstract: A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for sidebar communication threads forked from, or related to, a principal thread. Messages in the sidebar communication thread may include a history of the principal thread, including one or more messages from the principal thread, and may include a proposed principal thread message that is the subject of the sidebar thread discussion. The sidebar thread may also include sidebar thread messages that carries the conversation of the sidebar thread participants. Once a termination condition is reached for the sidebar thread, the sidebar thread terminates and either the proposed principal thread message (as potentially modified by participants of the sidebar thread) becomes an accepted principal thread message and it is posted to the principal thread as if it was sent by the sidebar initiator or no message is posted (e.g., the proposed principal thread message is rejected).