Abstract: A gate-controlled thyristor (GCT) and CAM memory are provided. The GCT includes first, second and third transistors, each having a control end, first and second ends. The control ends of the first and second transistors are connected to a search line. The control end of the second transistor is applied with a fixed bias voltage, and the second end of the second transistor is connected to the first end of the first transistor. The second end of the third transistor is connected to the first end of the second transistor, and the first end is connected to a match line. Based on the search line voltage, a search bit is determined to compare the data and the search bit to determine whether the search bit matches the data. This configuration may be applied to 3D NAND memory, having a high capacity and performance.

Abstract: Provided are a 3D memory and an operating method thereof. In the 3D memory, a stacked structure includes gate layers and insulating layers alternately stacked. Each gate layer includes first and second gates spaced from each other. Each annular channel layer corresponds to one of the gate layers and is disposed between adjacent insulating layers. A p-type doping region is disposed in each channel layer and adjacent to the first gate. An n-type doped region is disposed in each channel layer and adjacent to the second gate. A source line pillar penetrates through the stacked structure and contacts the n-type doped region. A bit line pillar penetrates through the stack structure and contacts the p-type doped region. A first gate insulation layer is disposed between the first gate and the channel layer. A second gate insulation layer is disposed between the second gate and the channel layer.

Abstract: A memory device based on thyristors, comprises the following elements. A plurality of gate structures, are continuous structures in the first direction. A plurality of bit lines, extending in a second direction substantially perpendicular to the first direction. A plurality of source lines, extending in the first direction. A plurality of channels, extending in a third direction substantially perpendicular to the first direction and the second direction, and penetrating the gate structures. The first doped regions of the channels are coupled to the bit lines, and the second doped regions of the channels are coupled to the source lines. A plurality of memory units formed by the gate structures and corresponding channels. The source lines are arranged in sequence according to the second direction to form a stair structure, and the lengths of the source lines decrease in sequence in the first direction.

Abstract: A computing-in-memory circuit including latches and NOR gates is provided. Each latch has a word line, a bit line, a complementary bit line, and first and second output ends. The bit line is coupled to a local bit line of one memory string in a memory array. The complementary bit line is coupled to a local complementary bit line of the memory string. The memory string includes storage units, each having a memory cell pair. The second output end provides a weight signal, sensed by the latch, from the memory cell. Each NOR gate has a first input end coupled to the second output end of the latch, a second input end receiving an external input signal, and an output end outputting a product of the weight and input signals.

Abstract: Provided are a 3D memory and an operating method thereof. In the 3D memory, a stacked structure includes gate layers and insulating layers alternately stacked. Each gate layer includes first and second gates spaced from each other. Each annular channel layer corresponds to one of the gate layers and is disposed between adjacent insulating layers. A p-type doping region is disposed in each channel layer and adjacent to the first gate. An n-type doped region is disposed in each channel layer and adjacent to the second gate. A source line pillar penetrates through the stacked structure and contacts the n-type doped region. A bit line pillar penetrates through the stack structure and contacts the p-type doped region. A first gate insulation layer is disposed between the first gate and the channel layer. A second gate insulation layer is disposed between the second gate and the channel layer.

Abstract: Provided are a three-dimensional (3D) flash memory and a manufacturing method thereof. The 3D flash memory includes a stacked structure, an annular channel pillar, first and second source/drain pillars, and a charge storage structure. The stacked structure is disposed on a dielectric substrate and includes a plurality of gate layers and a plurality of insulation layers alternately stacked. The insulation layer includes an air gap. The channel pillar is disposed on the dielectric substrate and penetrates through the stacked structure. The first and second source/drain pillars are disposed on the dielectric substrate, located inside the channel pillar, and penetrate through the stacked structure. The first and second source/drain pillars are separated from each other, and each is connected to the channel pillar. The charge storage structure is disposed between each of the gate layers and the channel pillar.

Abstract: A semiconductor device includes a substrate, a well region, a transistor device, and a memory device. The substrate includes a first region and a second region. The well region is located in the first region and the second region of the substrate. The transistor device is located in the well region of the first region. The memory device is located in the well region of the second region. The well region is continuous between the transistor device and memory device.

Abstract: A memory structure includes a substrate, a first gate structure, a second gate structure, a third gate structure, and channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along a first direction. The first gate structure, the second gate structure and the third gate structure are disposed on the substrate, and are separated from each other along the first direction and extend respectively along a second direction and a third direction. The first gate includes first, second and third island structures respectively extending along the third direction and separated from each other along the second direction. The third gate structure includes fourth, fifth and sixth island structures respectively extending along the third direction and separated from each other along the second direction.

Abstract: A gate-controlled thyristor (GCT) and CAM memory are provided. The GCT includes first, second and third transistors, each having a control end, first and second ends. The control ends of the first and second transistors are connected to a search line. The control end of the second transistor is applied with a fixed bias voltage, and the second end of the second transistor is connected to the first end of the first transistor. The second end of the third transistor is connected to the first end of the second transistor, and the first end is connected to a match line. Based on the search line voltage, a search bit is determined to compare the data and the search bit to determine whether the search bit matches the data. This configuration may be applied to 3D NAND memory, having a high capacity and performance.

Abstract: An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.

Abstract: A memory structure includes a substrate having an upper surface; a first gate structure and a second gate structure disposed on the substrate, separated from each other in a first direction and extend in a second direction, respectively; and a plurality of channel bodies separated from each other in the first direction and a third direction, and penetrating the first gate structure and the second structure, respectively. The first direction, the second direction and the third direction intersect each other. The upper surface is parallel to the first direction and the second direction, and a normal direction of the upper surface is parallel to the third direction. A first length of the first gate structure in the first direction and a second length of the second gate structure in the first direction are different from each other.

Abstract: A three-dimensional flash memory device may be a AND flash memory device. The three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of conductive pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.

Abstract: A head-mounted display device and a control method for an eye-tracking operation are provided. The head-mounted display device includes a frame, a track, a sensor and a controller. The track is disposed on a peripheral region of the frame. The sensor is disposed on the track, and is configured to capture a target image of a target area. The controller is coupled to the sensor, is configured to generate a control signal according to the target image, and adjust a position of the sensor on the peripheral region by moving the sensor according to the control signal.

Abstract: A memory structure includes a substrate; a first gate structure, a second gate structure and a third gate structure disposed on the substrate, separated from each other along the first direction and respectively extending along the second direction and the third direction; channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along the first direction; dielectric films disposed between the first gate structure, the second gate structure, the third gate structure and the channel bodies; and a first side plug electrically connected to the substrate and the channel bodies. The first gate structure, the second gate structure and the third gate structure surround each of the dielectric films and each of the channel bodies, and the dielectric films do not include a charge storage structure.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for sidebar communication threads forked from, or related to, a principal thread. Messages in the sidebar communication thread may include a history of the principal thread, including one or more messages from the principal thread, and may include a proposed principal thread message that is the subject of the sidebar thread discussion. The sidebar thread may also include sidebar thread messages that carries the conversation of the sidebar thread participants. Once a termination condition is reached for the sidebar thread, the sidebar thread terminates and either the proposed principal thread message (as potentially modified by participants of the sidebar thread) becomes an accepted principal thread message and it is posted to the principal thread as if it was sent by the sidebar initiator or no message is posted (e.g., the proposed principal thread message is rejected).

Abstract: A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for sidebar communication threads forked from, or related to, a principal thread. Messages in the sidebar communication thread may include a history of the principal thread, including one or more messages from the principal thread, and may include a proposed principal thread message that is the subject of the sidebar thread discussion. The sidebar thread may also include sidebar thread messages that carries the conversation of the sidebar thread participants. Once a termination condition is reached for the sidebar thread, the sidebar thread terminates and either the proposed principal thread message (as potentially modified by participants of the sidebar thread) becomes an accepted principal thread message and it is posted to the principal thread as if it was sent by the sidebar initiator or no message is posted (e.g., the proposed principal thread message is rejected).

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.