Patents by Inventor Wei-Chen Chen
Wei-Chen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11765901Abstract: Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. The first source/drain pillar and the second source/drain pillar are P-type doped.Type: GrantFiled: September 28, 2021Date of Patent: September 19, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hang-Ting Lue, Wei-Chen Chen
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Publication number: 20230269944Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.Type: ApplicationFiled: April 27, 2023Publication date: August 24, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Hang-Ting Lue, Wei-Chen Chen, Teng-Hao Yeh, Guan-Ru Lee
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Patent number: 11715444Abstract: Disclosed in some examples are display systems, methods, devices, and machine-readable mediums which provide for a gesture-based method for specifying a region of a display in which to show shared content. Also disclosed are pairing methods for associating the region of the display with a content source device, methods for sharing content within the region, and methods for providing input from the region back to the content source device. Also disclosed in some examples are display systems, methods, devices, and machine-readable mediums which provide for notification handling for user interfaces.Type: GrantFiled: June 22, 2022Date of Patent: August 1, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Amer Aref Hassan, Wei-Chen Chen
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Publication number: 20230240062Abstract: A memory structure includes a substrate; a first gate structure, a second gate structure and a third gate structure disposed on the substrate, separated from each other along the first direction and respectively extending along the second direction and the third direction; channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along the first direction; dielectric films disposed between the first gate structure, the second gate structure, the third gate structure and the channel bodies; and a first side plug electrically connected to the substrate and the channel bodies. The first gate structure, the second gate structure and the third gate structure surround each of the dielectric films and each of the channel bodies, and the dielectric films do not include a charge storage structure.Type: ApplicationFiled: May 18, 2022Publication date: July 27, 2023Inventors: Sheng-Ting FAN, Wei-Chen CHEN, Hang-Ting LUE
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Patent number: 11678486Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.Type: GrantFiled: February 6, 2020Date of Patent: June 13, 2023Assignee: MACRONIX INIERNATIONAL CO., LTD.Inventors: Hang-Ting Lue, Wei-Chen Chen, Teng Hao Yeh, Guan-Ru Lee
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Publication number: 20230097416Abstract: Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. The first source/drain pillar and the second source/drain pillar are P-type doped.Type: ApplicationFiled: September 28, 2021Publication date: March 30, 2023Inventors: Hang-Ting LUE, Wei-Chen CHEN
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Publication number: 20230070119Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.Type: ApplicationFiled: March 16, 2022Publication date: March 9, 2023Applicant: Macronix International Co., Ltd.Inventors: Hang-Ting Lue, Wei-Chen Chen, Teng-Hao Yeh
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Publication number: 20220408138Abstract: A mode switching method is applied to a display apparatus with a first scenario mode and a second scenario mode. The first scenario mode provides a first shortcut menu, and the second scenario mode provides a second shortcut menu different from the first shortcut menu. The mode switching method includes receiving a first signal source of a first external device, analyzing the first signal source to determine the first external device is matched with the first scenario mode or the second scenario mode, and displaying the first shortcut menu on a display interface of the display apparatus and hiding the second shortcut menu when the first external device is matched with the first scenario mode.Type: ApplicationFiled: December 1, 2021Publication date: December 22, 2022Applicant: BENQ CORPORATIONInventors: Li-Hsin Wu, Wei-Chen Chen, Cheng-En Wu, Hui-Chun Yang, Wei-Chung Hsu, Jheng-Ru He, En-Ming Kuo
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Patent number: 11514149Abstract: Disclosed in some examples are methods, systems and machine-readable mediums which allow for more secure authentication attempts by implementing authentication systems with credentials that include interspersed noise symbols in positions determined by the user. These systems secure against eavesdroppers such as shoulder-surfers or man-in-the middle attacks as it is difficult for an eavesdropper to separate the noise symbols from legitimate credential symbols.Type: GrantFiled: June 10, 2019Date of Patent: November 29, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Amer Aref Hassan, Wei-Chen Chen
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Patent number: 11496457Abstract: Systems and methods may be used for providing more secure authentication attempts by implementing authentication systems with credentials that include interspersed noise symbols in positions selected, for example by a user. These systems and methods secure against eavesdroppers such as shoulder-surfers or man-in-the middle attacks as it is difficult for an eavesdropper to separate the noise symbols from legitimate credential symbols. Some systems and methods may use a subset of a credential with the interspersed noise symbols.Type: GrantFiled: June 10, 2019Date of Patent: November 8, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Amer Aref Hassan, Wei-Chen Chen
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Publication number: 20220319469Abstract: Disclosed in some examples are display systems, methods, devices, and machine-readable mediums which provide for a gesture-based method for specifying a region of a display in which to show shared content. Also disclosed are pairing methods for associating the region of the display with a content source device, methods for sharing content within the region, and methods for providing input from the region back to the content source device.Type: ApplicationFiled: June 22, 2022Publication date: October 6, 2022Inventors: Amer Aref Hassan, Wei-Chen CHEN
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Publication number: 20220293628Abstract: A memory device includes a stack and a plurality of memory strings respectively penetrating the stack along the first direction and including adjacent ones of the first memory string and the second memory string. The first memory string and the second memory string include conductive pillars (including first to third conductive pillars), channel structures, and memory structures. The first memory string and the second memory string share the second conductive pillar. The channel structures include first to fourth channel layers respectively extending along the first direction. The first channel layer and the second channel layer correspond to the first memory string and are separated from each other. The third channel layer and the fourth channel layer correspond to the second memory string and are separated from each other. The memory structures are disposed between the stack and the channel structures.Type: ApplicationFiled: March 10, 2021Publication date: September 15, 2022Inventors: Wei-Chen Chen, Hang-Ting Lue
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Publication number: 20220254799Abstract: A semiconductor device is provided. The semiconductor device includes a first vertical stack, a first vertical channel line, a first data storage structure, and a first gate dielectric structure. The first vertical stack includes a first conductive line and a second conductive line. The first vertical channel line vertically passes through the first conductive line and the second conductive line, and the first vertical channel line is a P-type channel. The first data storage structure is disposed between the first conductive line and the first vertical channel line. The first gate dielectric structure is disposed between the second conductive line and the first vertical channel line.Type: ApplicationFiled: October 7, 2021Publication date: August 11, 2022Inventors: Hang-Ting LUE, Cheng-Lin SUNG, Wei-Chen CHEN
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Patent number: 11404028Abstract: Disclosed in some examples are display systems, methods, devices, and machine-readable mediums which provide for a gesture-based method for specifying a region of a display in which to show shared content. Also disclosed are pairing methods for associating the region of the display with a content source device, methods for sharing content within the region, and methods for providing input from the region back to the content source device.Type: GrantFiled: December 16, 2019Date of Patent: August 2, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Amer Aref Hassan, Wei-Chen Chen
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Publication number: 20220231041Abstract: A memory device includes a source element, a drain element, channel layers, control electrode layers, and a memory layer. The channel layers are individually electrically connected between the source element and the drain element. Memory cells are defined in the memory layer between the control electrode layers and the channel layers.Type: ApplicationFiled: January 15, 2021Publication date: July 21, 2022Inventors: Wei-Chen CHEN, Hang-Ting LUE
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Publication number: 20220064833Abstract: A thread feeding device of a sewing machine includes a needle bar movable vertically to pull an upper thread through a fabric, and movable between left and right terminal positions. An imaginary plane to which the needle bar is normal is defined, and includes left and right boundary lines which pass through the left and right terminal positions. An inner rotary hook includes a thread tensing unit disposed on a hook surrounding wall. A lower thread passes through and abuts against the thread tensing unit to define at least one thread abutting point. A final abutting point where the lower thread passes through the thread tensing unit immediately before reaching the fabric is defined, and is projected on the imaginary plane at a point that is interposed between the boundary lines.Type: ApplicationFiled: March 31, 2021Publication date: March 3, 2022Applicant: ZENG HSING INDUSTRIAL CO., LTD.Inventors: Wei-Chen CHEN, Po-Hsien TSENG, Ching-Lin HUANG, Li CHIANG
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Publication number: 20220068922Abstract: A memory structure is provided. The memory structure includes a first channel body, a first source region, a first drain region, a first gate structure and a second gate structure. The first source region has a first conductivity and connects to a first end of the first channel body. The first drain region has a second conductivity and connects to a second end of the first channel body separated from the first end. The first gate structure is disposed adjacent to the first channel body and between the first end and the second end. The second gate structure disposed adjacent to the first channel body and between the first end and the second end.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Wei-Chen CHEN, Hang-Ting LUE
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Patent number: 11258783Abstract: Disclosed in some examples are methods, systems and machine-readable mediums which allow for more secure authentication attempts by implementing authentication systems with credentials that include interspersed noise symbols in positions determined by the user. These systems secure against eavesdroppers such as shoulder-surfers or man-in-the middle attacks as it is difficult for an eavesdropper to separate the noise symbols from legitimate credential symbols.Type: GrantFiled: June 10, 2019Date of Patent: February 22, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Amer Aref Hassan, Wei-Chen Chen
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Patent number: 11240227Abstract: Systems and methods may be used for providing more secure authentication attempts by implementing authentication systems with credentials that include interspersed noise symbols in positions selected, for example by a user. These systems and methods secure against eavesdroppers such as shoulder-surfers or man-in-the middle attacks as it is difficult for an eavesdropper to separate the noise symbols from legitimate credential symbols. Some systems and methods may use a subset of a credential with the interspersed noise symbols.Type: GrantFiled: June 10, 2019Date of Patent: February 1, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Amer Aref Hassan, Wei-Chen Chen
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Patent number: 11178135Abstract: Systems and methods may be used for providing more secure authentication attempts by implementing authentication systems with credentials that include interspersed noise symbols in positions selected, for example by a user. These systems and methods secure against eavesdroppers such as shoulder-surfers or man-in-the middle attacks as it is difficult for an eavesdropper to separate the noise symbols from legitimate credential symbols. Some systems and methods may use a subset of a credential with the interspersed noise symbols.Type: GrantFiled: June 10, 2019Date of Patent: November 16, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Amer Aref Hassan, Wei-Chen Chen