Abstract: A method of manufacturing an image sensor structure includes forming an isolation structure in a substrate to divide the substrate into a first region and a second region, forming a first light sensing region in the first region and a second light sensing region in the second region, forming a first gate structure over the first light sensing region and a second gate structure over the second light sensing region, forming gate spacers on sidewalls of the first and second gate structures, and depositing a blocking layer on sidewalls of the gate spacers. The blocking layer has an opening positioned between the first and second gate structures. A source/drain structure is formed directly under the opening in the blocking layer. The method also includes forming an interlayer dielectric layer over the first and second gate structures and the blocking layer.

Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A hard disk bracket configured to be installed on a case includes a tray, a base, a handle, a pin, and a latch. The tray has an accommodating space. The base is connected to the tray. The handle is disposed in the base and has a first slide part detachably fastened with the base. The pin is disposed through the handle and the base. The latch is disposed in the base and is detachably fastened with the case. The latch is fastened with the handle and has a second slide part penetrating the handle for extending outside the base.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: A visual inspection method of a curved object executed by a visual inspection system. The visual inspection system includes a robotic arm, a camera mounted at a tail end of the robotic arm, a fixing unit mounted under the camera, and a control unit electrically connected to the robotic arm and the camera. Specific steps of the visual inspection method of the curved object are described hereinafter. Fix a curved object which is to be inspected by the fixing unit. Capture the object which is to be inspected with a plurality of groups of preset parameters by the camera. Use the control unit to calculate a better shooting parameter. Use the better shooting parameter by the camera to proceed with visual inspections of the curved objects which are to be inspected in batches.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

Abstract: A system and method for maximizing bandwidth in an uplink for a 5G communication system is disclosed. Multiple end devices generate image streams. A gateway is coupled to the end devices. The gateway includes a gateway monitor agent collecting utilization rate data of the gateway and an image inspector collecting inspection data from the received image streams. An edge server is coupled to the gateway. The edge server includes an edge server monitor agent collecting utilization rate data of the edge server. An analytics manager is coupled to the gateway and the edge server. The analytics manager is configured to determine an allocation strategy based on the collected utilization rate data from the gateway and the edge server.

Abstract: A head-mounted display device includes a body, two adjustment rings, and a face gasket. The body has two zoom lens groups corresponding to both eyes. The two adjustment rings are used to be detachably assembled to the corresponding zoom lens group, respectively. The face gasket is used to be detachably assembled to the body and used to contact a user's face. The face gasket has two adjustment knobs. Each of the adjustment knobs is used to couple the corresponding adjustment ring and rotate the corresponding zoom lens group for zooming, and a part of the each of the adjustment knobs is exposed to the outside for the user to manipulate.

Abstract: A head mounted display device including a host, a first bracket and a second bracket is provided. The opposite sides of the host respectively have a first connection port and a second connection port. The first bracket is detachably and electrically connected to the first connection port. The second bracket is detachably connected to the second connection port.

Abstract: A head mounted display device including a host, two brackets, and two rotating components is provided. The two brackets are respectively pivotally connected to opposite sides of the host. Each bracket includes a first segment and a second segment. The first segment is pivotally connected to the second segment, and the first segment is pivotally connected to the host. The two rotating components are respectively assembled to the first segment and the second segment of each bracket to control an angle between the first segment and the second segment.

Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.

Abstract: An Internet of Things (IoT) system includes an application server, an identification information server, a gateway, and a terminal electronic device. The identification information server is configured to generate a plurality of pieces of first identification information, and each piece of first identification information is time-sensitive. The gateway is connected to the application server and stores the pieces of first identification information. The gateway is configured to automatically determine a piece of valid identification information from the pieces of first identification information. The terminal electronic device stores the pieces of first identification information and is configured to automatically and successively select a piece of current identification information from the pieces of first identification information to establish a connection with the gateway.

Abstract: A neck-mounted power bank is suitable for being hung on a user's neck to supply power to an electronic device. The neck-mounted power bank includes a body, a battery, and a pair of adjustable assemblies. The battery is disposed in the body. The pair of adjustable assemblies are respectively connected to two ends of the body, and define a wearing space with the body. The pair of adjustable assemblies can be rotated relative to the body so as to adjust the size of the wearing space. Each of the pair of adjustable assemblies includes a rotate arm and an angle arm. The rotate arm is rotatably connected to a corresponding end of the body. The angle arm is connected to the rotate arm and has a contact surface. The contact surface is suitable for contacting the user's neck.

Abstract: A neck-mounted power bank includes a neck-mounted portion, a first body and a second body. The first body is connected to an end of the neck-mounted portion. The second body is connected to another end of the neck-mounted portion. The neck-mounted portion, the first body and the second body define a wearing space. The first body includes a first tray and a first controller. The first tray is connected to the neck-mounted portion. The first controller is detachable and electrically connected to the first tray, and has a first controller battery. When the first controller is installed and electrically connected to the first tray, the first controller battery can supply power to an electronic device through the first tray. When the first controller is detached from the first tray, the first controller can control the electronic device wirelessly.