Patents by Inventor Wei-Chi Cheng

Wei-Chi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170323852
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Application
    Filed: June 2, 2016
    Publication date: November 9, 2017
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20170294508
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.
    Type: Application
    Filed: May 3, 2016
    Publication date: October 12, 2017
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
  • Patent number: 9735047
    Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 15, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Yu Chang, Ssu-I Fu, Yu-Hsiang Hung, Chih-Kai Hsu, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 9711394
    Abstract: A method for fabricating a semiconductor device includes the following steps: providing a substrate having an epitaxial layer, a gate structure and an interlayer dielectric thereon, where the epitaxial structure is disposed at sides of the gate structure and the interlayer dielectric covering the epitaxial structure; forming an opening in the interlayer dielectric so that the surface of the epitaxial layer is exposed from the bottom of the opening; performing a rapid thermal process in an inert environment until non-conductive material is generated on the surface of the epitaxial layer; and removing the non-conductive material.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chih-Kai Hsu, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 9685385
    Abstract: The present invention provides a method for forming a semiconductor device, including the following steps: first, a substrate is provided, at least one gate is formed on the substrate, a contact etching stop layer (CESL) and a first dielectric layer are formed on the substrate in sequence, afterwards, a first etching process is performed to remove the first dielectric layer, and to expose a top surface and at least one sidewall of the etching stop layer, next, a second etching process is performed to partially remove the contact etching stop layer, and to form at least one epitaxial recess in the substrate. Afterwards, an epitaxial process is performed, to form an epitaxial layer in the epitaxial recess, and a contact structure is then formed on the epitaxial layer.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chih-Kai Hsu, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Publication number: 20160358827
    Abstract: A method of forming a fin-shaped structure includes the following step. A substrate having a first area and a second area is provided. An epitaxial structure is formed in the first area. An epitaxial structure is formed in the second area after the epitaxial structure in the first area is formed, wherein the surface area of the epitaxial structure in the first area is different from the surface area of the epitaxial structure in the second area.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq