Abstract: A vibration module is installed in a touch plate. The vibration module includes a housing, a magnetic element, a coil layer and a base plate. The housing includes an accommodation space and an elastic structure. The magnetic element and the coil layer are aligned with each other and disposed within the accommodation space. The base plate is connected with the housing. In addition, the magnetic element and the coil layer are sealed in the accommodation space. The base plate is connected with the housing to seal the magnetic element and the coil layer in the accommodation space. The elastic structure is extended in the direction toward the accommodation space and connected with the magnetic element. The magnetic element is pushed to be close to the coil layer by the elastic structure. When the coil layer is electrically conducted, the magnetic element senses the coil layer and vibrates.

Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.

Abstract: An antenna structure and an electronic device are proposed. The antenna structure includes a feeding source, a main radiation portion, a grounding portion and a floating portion. The main radiation portion is connected to the feeding source and extends toward a first direction. The grounding portion is connected to a grounding layer, and a first gap is formed between the grounding portion and the main radiation portion. The grounding portion extends toward the first direction. A second gap is formed between the floating portion and the grounding portion. The floating portion extends toward the first direction. The main radiation portion, the grounding portion and the floating portion are arranged sequentially along a second direction.

Abstract: A sensing module includes a first antenna unit, a second antenna unit, a first inductor and a proximity sensor. The first antenna unit has at least one first communication frequency band, and the second antenna unit has at least one second communication frequency band. The first antenna unit and the second antenna unit are connected in parallel to one end of the first inductor, and the other end of the first inductor is electrically connected to the proximity sensor.

Abstract: A method for controlling a plurality of mobile robots is to be implemented by a server that communicates with the plurality of mobile robots and a communication device. The server stores a predetermined working route related to a target area. The method includes steps of: receiving a working instruction from the communication device, the working instruction including area information related to the target area and an input quantity of mobile robots; in response to receipt of the working instruction, dividing the predetermined working route into a plurality of sub-routes, wherein a quantity of the sub-routes equals the input quantity of mobile robots; and sending the sub-routes respectively to a plurality of selected robots that are selected from among the plurality of mobile robots to make the selected robots cooperatively implement a task on the target area by moving along the sub-routes, respectively.

Abstract: A bonding structure and a pre-bonding structure are provided. The bonding structure includes a lower substrate; a low melting point conductive layer disposed over the lower substrate; a high melting point conductive layer including a lower portion and an upper portion, wherein the low melting point conductive layer is between the upper portion and the lower portion of the high melting point conductive layer; a dielectric layer encapsulating the low melting point conductive layer and the high melting point conductive layer; and an upper substrate disposed on the upper portion of the high melting point conductive layer, wherein an interface between the upper substrate and the high melting point conductive layer is substantially co-level with an interface between the dielectric layer and the upper substrate.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: A semiconductor device includes a plurality of active regions extending in a first direction. The semiconductor device further includes a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction. The semiconductor device further includes a power rail extending in the first direction. The power rail includes a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.

Abstract: A method for calibrating sensed force of a touch pad module is provided. The touch pad module includes a touch pad and force sensing elements disposed therebeneath. The method includes: obtaining a force reference table obtained before the touch pad module is assembled with an electronic device, the force reference table including a first data, which includes a first point of the touch pad and first force reference values corresponding to the first point and respectively corresponding to the force sensing elements; placing a calibration block on the first point after the touch pad module is assembled with the electronic device, so the force sensing elements respectively obtain first force test values corresponding to the first point; calculating first compensation ratios according to the first force reference values and the first force test values; and inputting the first compensation ratios into the force reference table.

Abstract: In the present invention, an earthquake detection system based on the combination configuration of a free field and remote signal source is provided. The earthquake detection system includes: a host; a main sensor arranged in a free field and connected to the host; and a plurality of backup sensors, which are remotely arranged with respect to the main sensor, wherein each of the backup is connected to the host via the internet and transmits a remote signal to the host so as to avoid misjudging the occurrence of earthquakes because of unnatural factors, and prevent the vibration caused by human activities from interfering with the detector. The earthquake detection system achieves the effect of verification through a plurality of sensors installed in different positions.

Abstract: An integrated circuit is provided, including a first conductive pattern, at least one first conductive segment, and a first via. The first conductive pattern is disposed in a first layer and configured as a terminal of an inverter. The at least one first conductive segment is disposed in a second layer above the first layer and configured to transmit an output signal output from the inverter. The first via contacts the first conductive pattern and the at least one first conductive segment to transmit the output signal. An area, contacting the first conductive pattern, of the first via is smaller than an area, contacting the at least one first conductive segment, of the first via.

Abstract: A power supplying circuit and an associated switch controller for a non-volatile memory are provided. When the sector erase is performed, the voltage stress withstood by the switching transistors in the power supplying circuit is lower than the maximum voltage stress. In addition, the voltage stress withstood by all transistors in the switch controller is lower than the maximum voltage stress. In other words, when the sector erase is performed, all switch controllers and all switching transistors in the power supplying circuit can be operated normally. In addition, an erase voltage is provided to a specified sector of the array structure, so that all memory cells in the specified sector are erased into the erase state.

Abstract: A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.

Abstract: A semiconductor device includes a fin structure, a source/drain region, a first inter-layer dielectric (ILD) layer, a first contact plug, and a second contact plug. The fin structure extends above a substrate. The source/drain region is in the fin structure. The first ILD layer is over the source/drain region. The first contact plug extends through the first ILD layer to a silicide region of the source/drain region. The second contact plug is over the first contact plug. The first contact plug has a protruding portion extending above the first ILD layer and laterally surrounding a lower part of the second contact plug.

Abstract: An electronic device includes a chassis, a primary system board mounted to the chassis, first and second connectors, and a set of support members coupled to the chassis. The first connector is directly mounted and electrically connected to the primary system board, and includes first and second support walls, and a first pin protruding from the first support wall. The second connector includes a cable electrically connected to the primary system board, and includes third and fourth support walls, a first hole formed in the third support wall, and a second hole formed in the fourth support wall. A support member of the set of support members includes a second pin. The first pin protrudes into the first hole to couple the second connector to the first connector, and the second pin protrudes into the second hole to further couple the second connector to the first support member.

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions arranged on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Abstract: A method of manufacturing a transmission gate includes overlying a substrate with first through fourth adjacent metal segments in a same metal layer. Each of the first and second metal segments, second and third metal segments, and third and fourth metal segments are offset from each other by an offset distance in a first direction, the first metal segment overlies a first active area in the substrate including first and second PMOS transistors, and the fourth metal segment overlies a second active area in the substrate including first and second NMOS transistors. The method includes configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming first through third conductive paths, the first conductive path including a fifth metal segment overlying at least three of the first through fourth metal segments along a second direction perpendicular to the first direction.

Abstract: A method for controlling a plurality of autonomous robots for performing environment maintenance operations includes: generating a setup command that indicates a selected location, a plurality of selected robots, an available time slot, and a distribution mode signal that indicates whether the selected robots are to be controlled based on the available time slot or an inputted priority section; and generating a plurality of sub-routes based on different parameters, depending on the distribution mode signal. The sub-routes are generated to be connected into an unbroken trail. Then, the sub-routes are transmitted to the selected robots, respectively, so as to control each of the selected robots to move along the respective one of the sub-routes.

Abstract: Systems and methods for retinal imaging are provided. A heads-up display (HUD) can be integrated with advanced retinal imaging modalities, including optical coherence tomography (OCT) and fundoscopy (e.g., fluorescence fundoscopy). The HUD can serve as a crucial component of this approach, offering several key functionalities (e.g., a fixation target and/or a means for dark adaptation).