Abstract: A touch module includes a base plate, a magnet, a touchpad and a magnetic board. The magnetic board includes a first sensing line, a second sensing line, a third sensing line, a first communication part and a second communication part. The touchpad is located over the base plate. The magnetic board is arranged between the touchpad and the magnet. The first sensing line, the second sensing line and the third sensing line of the magnetic board are in parallel with each other and stacked on each other. The first sensing line is electrically connected with the second sensing line through the first communication part. The second sensing line is electrically connected with the third sensing line through the second communication part. The first sensing line, the second sensing line and the third sensing line sense a magnetic field of the magnet and generates a vibration.

Abstract: A touch feedback correction method and a touch module using the touch feedback correction method are provided. In the touch feedback correction method, the coordinate values and the initial vibration values of plural press region on a touch panel of the touch module are detected. Consequently, a driving voltage calibration table is established. Then, a vibrating unit of the touch module is driven according to plural compensated voltage values of the driving voltage calibration table. Consequently, the plural press regions generate plural corrected vibration values, respectively.

Abstract: A semiconductor device includes a bottom electrode via, a top electrode via over the bottom electrode via, a memory cell between the bottom electrode via and the top electrode via, a first dielectric layer over the memory cell, and a second dielectric layer over the first dielectric layer, and a via structure separated from the memory cell. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell, and a height of the top electrode via. The first dielectric layer partially surrounds a first portion of the via structure, and the second dielectric layer partially surrounds a second portion of the via structure. A height of the second portion of the via structure is greater than a height of the first portion of the via structure.

Abstract: A touchpad module includes a base plate, a touch member, a supporting structure and a pressure sensing unit. The touch member is movable toward the base plate. The supporting structure is arranged between the base plate and the touch member. The pressure sensing unit is installed on the touch member. The pressure sensing unit is arranged between the touch member and the base plate. While the touch member is pressed in response to an external pressing force, the touch member is moved downwardly toward the base plate to compress the supporting structure. Consequently, the supporting structure is subjected to deformation, and the touch member has a displacement amount. According to the displacement amount, a magnitude of the pressing force is sensed by the pressure sensing unit, and a pressure sensing signal is outputted from the pressure sensing unit.

Abstract: A method for controlling a plurality of autonomous robots for performing environment maintenance operations includes: generating a setup command that indicates a selected location, a plurality of selected robots, an available time slot, and a distribution mode signal that indicates whether the selected robots are to be controlled based on the available time slot or an inputted priority section; and generating a plurality of sub-routes based on different parameters, depending on the distribution mode signal. The sub-routes are generated to be connected into an unbroken trail. Then, the sub-routes are transmitted to the selected robots, respectively, so as to control each of the selected robots to move along the respective one of the sub-routes.

Abstract: A method for controlling a plurality of mobile robots is to be implemented by a server that communicates with the plurality of mobile robots and a communication device. The server stores a predetermined working route related to a target area. The method includes steps of: receiving a working instruction from the communication device, the working instruction including area information related to the target area and an input quantity of mobile robots; in response to receipt of the working instruction, dividing the predetermined working route into a plurality of sub-routes, wherein a quantity of the sub-routes equals the input quantity of mobile robots; and sending the sub-routes respectively to a plurality of selected robots that are selected from among the plurality of mobile robots to make the selected robots cooperatively implement a task on the target area by moving along the sub-routes, respectively.

Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second transistor disposed over the first transistor, and a conductive trace. The first transistor includes first conductive segments, corresponding to drain and source terminals of the first transistor and extending in a first direction, on a first layer. The second transistor includes second conductive segments, corresponding to drain and source terminals of the second transistor and extending in the first direction, on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in the first direction, and the third layer is interposed between the first and second layers. The first conductive segments, the second conductive segments, and the conductive trace overlap in a layout view.

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

Abstract: A package includes a substrate, a first light-emitting unit, a second light-emitting unit, a light-transmitting layer, and a light-absorbing layer. The substrate has a first surface and an upper conductive layer on the first surface. The first light-emitting unit and the second light-emitting unit are disposed on the upper conductive layer. The first light-emitting unit has a first light-emitting surface and a first side wall. The second light-emitting unit has a second light-emitting surface and a second side wall. The light-transmitting layer is disposed on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit. The light-absorbing layer is disposed between the substrate and the light-transmitting layer, covers the upper conductive layer, the first side wall, and the second side wall, and exposes the first light-emitting surface and the second light-emitting surface.

Abstract: An electronic device and an antenna structure thereof are provided. The antenna structure includes a first, a second and a third radiating element and a grounding element. The first radiating element includes a first and a second radiating portion, a feeding portion and a grounding portion. The grounding portion includes a first, a second, a third, a fourth and a fifth section. The first section is connected between the first radiating portion and the feeding portion. The grounding element is connected with the fourth section and the fifth section. The second radiating element is connected with the grounding element. The second radiating element includes a third radiating portion, and the third and the second radiating portion are coupled with each other. The third radiating element is connected with the feeding portion, and the third radiating element and the first section are coupled with each other.

Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

Abstract: A light-emitting unit, having a substrate; a first light-emitting body formed on the substrate, and having a first longer side and a first shorter side; a second light-emitting body formed on the substrate, and having a second longer side and a second shorter side which is parallel to the first longer side; a third light-emitting body formed on the substrate, having a third longer side and a third shorter side which is parallel to the first longer side, and electrically connected to the first light-emitting body and the second light-emitting body; a first electrode covering the first light-emitting body and the second light-emitting body, and electrically connecting to the first light-emitting body; a second electrode separated from the first electrode, and covering the second light-emitting body without covering the first light-emitting body; and a transparent element enclosing the first light-emitting body, the second light-emitting body, and the third light-emitting body.

Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

Abstract: A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium. The method includes generating the layout diagram using an electronic design system (EDS), the EDS including at least one processor and at least one memory including computer program code for one or more programs are configured to cause the EDS to execute the generating. Testing the semiconductor device. Revising, the layout diagram, based on testing results indicative of selected standard functional cells in the layout diagram which merit modification or replacement. Programming one or more of the ECO cells which correspond to the one or more selected standard functional cells resulting in one or more programmed ECO cells. Routing the one or more programmed ECO cells correspondingly to at least one of the selected standard functional cells or to one or more other ones of the standard functional cells.

Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.