Patents by Inventor Wei Chih Chen

Wei Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791313
    Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • Publication number: 20230326822
    Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Inventors: Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11768516
    Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Wei Chih Chen
  • Publication number: 20230282558
    Abstract: A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Sih-Hao Liao, Wei-Chih Chen, Hung-Chun Cho, Ting-Chen Tseng, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11739784
    Abstract: A method for forming a stop flange on a self-tapping screw includes locating a shank of a self-tapping screw between two threading dies, fixing one of the two threading dies and moving the other one of the two threading dies to work the shank, the external thread forming section of each of the threading dies performing threading to form an external thread on the shank, inserting the insert and the recessed corner of each of the threading dies into a top of the external thread to form a groove in the shank, and the insert of each of the threading dies gradually squeezing downward an extruded portion that is formed during formation of the groove to form a stop flange on the shank. Thus, the shank is integrally formed with the stop flange, to stop an excessive movement of the external thread.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: August 29, 2023
    Inventor: Wei-Chih Chen
  • Patent number: 11725684
    Abstract: A screw structure includes a screw and a washer mounted on the screw. The bottom face of the screw head is provided with a plurality of pressing portions. Each of the pressing portions has a top provided with a first plane and a bottom provided with a second plane having an area smaller than that of the first plane. Each of the pressing portions is provided with a first inclined face and a first steep arcuate face. The first inclined face is directed toward a clockwise direction of the screw when the screw is screwed. The first steep arcuate face is directed toward the external thread. When the screw is screwed into an article, the pressing portions press the washer, and an outer diameter of the washer is expanded outward and forms an expansion.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: August 15, 2023
    Inventor: Wei-Chih Chen
  • Publication number: 20230251519
    Abstract: An electronic device includes: a first substrate; a second substrate opposite to the first substrate; a black matrix layer disposed between the first and second substrates and including a first pixel region and a first shielding region arranged along a first direction, wherein the first pixel region includes first and sub-pixel openings arranged along a second direction different from the first direction; a scan line disposed between the first and second substrates and extending along the second direction, wherein the first shielding region overlaps the scan line; and first and second pixel color resists respectively disposed corresponding to the first and second sub-pixel openings, wherein in a cross-sectional view, a recess is formed between the first pixel color resist and the second pixel color resist, the recess is disposed in the first pixel region, and the recess comprises a curved side wall.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 10, 2023
    Inventors: Wei-Chih CHEN, Chih-Ming LIANG
  • Patent number: 11721603
    Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230223357
    Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.
    Type: Application
    Filed: May 24, 2022
    Publication date: July 13, 2023
    Inventors: Yi-Che Chiang, Chien-Hsun Chen, Tuan-Yu Hung, Hsin-Yu Pan, Wei-Kang Hsieh, Tsung-Hsien Chiang, Chao-Hsien Huang, Tzu-Sung Huang, Ming Hung Tseng, Wei-Chih Chen, Ban-Li Wu, Hao-Yi Tsai, Yu-Hsiang Hu, Chung-Shi Liu
  • Publication number: 20230204652
    Abstract: A voltage sensor system for determining an abnormal circuit condition in a multi-layer printed circuit board is disclosed. The printed circuit board has a plurality of layers. One of the layers includes a trace network and a sensor circuit. The sensor circuit includes the trace network and a sensing point. The sensor circuit is coupled between a voltage supply and a ground. A controller is coupled to the sensing point. The controller is operable to determine a voltage of the sensing point and compare the voltage to a threshold value to determine an abnormal circuit condition in the printed circuit board.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Inventors: Yangtzu LEE, Wei-Chih CHEN, Pin-Hao HUNG
  • Publication number: 20230187318
    Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 15, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
  • Publication number: 20230185349
    Abstract: An embodiment of an integrated circuit may comprise a circuit block and a power management circuit coupled to the circuit block to manage two or more power states for the circuit block and to manage a request for the circuit block to enter a requested power state of the two or more power states, set a watchdog timer in response to the request, and monitor the watchdog timer and a transition of the circuit block from a current power state to the requested power state. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Applicant: Intel Corporation
    Inventors: Wei Chih Chen, Thiam Wah Loh, Wei Shun Chang
  • Publication number: 20230176638
    Abstract: An electronic device for switching a standby power of a motherboard includes a universal serial bus (USB) connector, electrically connected to the motherboard, configured to connect an external device; a device detecting module, coupled to the USB connector, configured to determine a power control signal according to a voltage level of the USB connector; and an output switching control module, coupled to the device detecting module and the USB connector, configured to determine whether to cut off the standby power provided by the motherboard to the USB connector or not according to the power control signal.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 8, 2023
    Applicant: Wiwynn Corporation
    Inventors: Hao-Chuan Chu, Kuo-Hua Tsai, Che-Wei Lin, Wei-Chih Chen, Po-Lin Huang, Chia-Hui Chen
  • Patent number: 11656492
    Abstract: An electronic device includes: a first substrate; a second substrate opposite to the first substrate; a black matrix layer disposed between the first and second substrates and including a first pixel region and a first shielding region disposed along a first direction, wherein the first pixel region includes a first sub-pixel opening; a scan line disposed between the first and second substrates and extending along a second direction different from the first direction, wherein the first shielding region overlaps the scan line; and a first color resist and a second color resist disposed in the fielding region, having different colors and overlapping each other to form an overlapping region, wherein a width of the overlapping region at the second direction is greater than or equal to 0 and less than 50% of a width of the first sub-pixel opening at the second direction.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: May 23, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Chih Chen, Chih-Ming Liang
  • Publication number: 20230118709
    Abstract: A method for detecting an undesired connection forming a short circuit on a printed circuit board (PCB) based on an original image of the PCB includes steps of: performing binarization on the original image to generate a binary image that has an external boundary; determining, on the binary image, a trace area that corresponds to a trace of the PCB; determining whether the trace area contacts the external boundary of the binary image at four places; and determining that the trace that corresponds to the trace area has an undesired connection forming a short circuit when it is determined that the trace area contacts the external boundary of the binary image at four places.
    Type: Application
    Filed: July 26, 2022
    Publication date: April 20, 2023
    Applicant: National Tsing Hua University
    Inventors: Ming-Tsang LEE, Wei-Chih CHEN, Jia-Wei LU, Yu-Bin CHEN
  • Patent number: 11628320
    Abstract: A fall arrest connector is used to connect at least a safety belt with a snap hook and a wearable harness for a user to wear. The fall arrest connector includes a retaining ring, a buckle ring, and a breakable connection. The retaining ring, including the first connecting portion, is connected to the wearable harness. The buckle ring, including the second connecting portion, is hooked by the snap hook. The breakable connection connects the second connecting portion and the first connecting portion. When the retaining ring or the buckle ring is pulled by a predetermined external force, the breakable connection is broken to separate the first and the second connecting portion. The retaining ring and the buckle ring could respectively be connected to the substitute protection device, which could provide the user an instant protection when the first connecting portion and the second connecting portion are separated.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: April 18, 2023
    Assignee: YOKE INDUSTRIAL CORP.
    Inventors: Wei-Chieh Hung, Wei-Chih Chen, Tzu-Lun Weng
  • Patent number: 11624392
    Abstract: A thrust screw assembly includes a thrust screw and two threading dies for working the thrust screw. The thrust screw includes a first shank, a second shank, an external thread, and a thrust member. Each of the threading dies is provided with an external thread forming section and a flat portion forming section. In a first molding process, the first shank is worked to form the thrust member with two wing-shaped stop pieces. In a second molding process, the second shank is processed by the external thread forming section of each of the two threading dies to form the external thread on the second shank, and the two wing-shaped stop pieces is processed by the flat portion forming section of each of the two threading dies to form two flat portions on the two wing-shaped stop pieces simultaneously.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: April 11, 2023
    Inventor: Wei-Chih Chen
  • Publication number: 20230107825
    Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventor: Wei Chih Chen
  • Patent number: 11609261
    Abstract: A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 21, 2023
    Assignee: CHROMA ATE INC.
    Inventors: Wei-Chih Chen, Ben-Mou Yu, Yi-Yen Lin
  • Publication number: 20230061473
    Abstract: A screw structure includes a screw and a washer mounted on the screw. The bottom face of the screw head is provided with a plurality of pressing portions. Each of the pressing portions has a top provided with a first plane and a bottom provided with a second plane having an area smaller than that of the first plane. Each of the pressing portions is provided with a first inclined face and a first steep arcuate face. The first inclined face is directed toward a clockwise direction of the screw when the screw is screwed. The first steep arcuate face is directed toward the external thread. When the screw is screwed into an article, the pressing portions press the washer, and an outer diameter of the washer is expanded outward and forms an expansion.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Inventor: Wei-Chih Chen