Patents by Inventor Wei Chih Chen

Wei Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220233897
    Abstract: A fall arrest connector is used to connect at least a safety belt with a snap hook and a wearable harness for a user to wear. The fall arrest connector includes a retaining ring, a buckle ring, and a breakable connection. The retaining ring, including the first connecting portion, is connected to the wearable harness. The buckle ring, including the second connecting portion, is hooked by the snap hook. The breakable connection connects the second connecting portion and the first connecting portion. When the retaining ring or the buckle ring is pulled by a predetermined external force, the breakable connection is broken to separate the first and the second connecting portion. The retaining ring and the buckle ring could respectively be connected to the substitute protection device, which could provide the user an instant protection when the first connecting portion and the second connecting portion are separated.
    Type: Application
    Filed: January 25, 2021
    Publication date: July 28, 2022
    Applicant: YOKE INDUSTRIAL CORP.
    Inventors: WEI-CHIEH HUNG, WEI-CHIH CHEN, TZU-LUN WENG
  • Publication number: 20220208711
    Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11367637
    Abstract: A method of operating a transport system includes detecting an anomalous condition of a wafer transfer vehicle; sending the wafer transfer vehicle along a rail to a diagnosis station adjacent to the rail; and inspecting properties of the wafer transfer vehicle, such as a speed, a weight, an audio frequency, a noise level, a temperature, and an image of the wafer transfer vehicle, by using the diagnosis station.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Yuan Chu, Jen-Ti Wang, Wei-Chih Chen, Kuo-Fong Chuang, Cheng-Ho Hung
  • Publication number: 20220189854
    Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a via, an encapsulant, an adhesion promoter layer, and a polymer layer. The via is laterally aside the die. The encapsulant laterally encapsulates the die and the via. The adhesion promoter layer is sandwiched between the via and the encapsulant. The encapsulant comprises a portion aside the via and under the adhesion promoter layer, and the portion of the encapsulant is sandwiched between the adhesion promoter layer and the polymer layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
  • Patent number: 11348817
    Abstract: A wafer transport device is moved on a transport rail, and stopped above a load port having a top surface. A light beam is projected onto the top surface of the load port, and image of the top surface is and the light beam is captured. A position of the hoist unit of the wafer transport device is aligned with respect to a position of the load port according to the image. The hoist unit is lowered toward the load port.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chih Chen, Shi-Chi Chen, Ting-Wei Wang, Jen-Ti Wang, Kuo-Fong Chuang
  • Patent number: 11342296
    Abstract: A semiconductor structure includes an insulating encapsulant, a semiconductor element, a redistribution layer and an insulating layer. The semiconductor element is embedded in the insulating encapsulant. The redistribution layer is disposed over the insulating encapsulant and electrically connected to the semiconductor element. The insulating layer is disposed in between the insulating encapsulant and the redistribution layer, wherein an uneven interface exists between the insulating layer and the insulating encapsulant, and a planar interface exists between the insulating layer and the redistribution layer.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Patent number: 11330416
    Abstract: A method applied into a controller of a wireless Bluetooth device includes: providing a first flag and a second flag; asserting the first flag when the controller successfully receives the particular packet transmitted from the audio gateway; asserting the second flag when the controller successfully receives an acknowledgement from a secondary device wherein a reception of the acknowledgement indicates that the secondary device successfully receives the particular packet; and transmitting an acknowledgement of a particular packet to an audio gateway when the first flag and the second flag are asserted.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: May 10, 2022
    Assignee: Audiowise Technology Inc.
    Inventors: Chih-Wei Sung, Pete Hsinhsiang Liu, Jing-Syuan Jia, Wei-Chung Peng, Kuang-Hu Huang, Jeng-Hong Chen, I-Ken Ho, Wei-Chih Chen, De-Hao Tseng
  • Publication number: 20220139725
    Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.
    Type: Application
    Filed: April 30, 2021
    Publication date: May 5, 2022
    Inventors: Wei-Chih Chen, Yu-Hsiang Hu, Hung-Jui Kuo, Sih-Hao Liao
  • Publication number: 20220135723
    Abstract: The present invention provides a polyvinyl alcohol graft copolymer including a polyvinyl alcohol main chain. The polyvinyl alcohol graft copolymer includes branched chains including structural units derived from the following monomers: (a) a fluorine-including ethylenically unsaturated monomer, (b) an ethylenically unsaturated carboxylic acid monomer, and (c) an ethylenically unsaturated amide monomer. The present invention also provides an aqueous binder composition, and an electrode slurry composition including the polyvinyl alcohol graft copolymer.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 5, 2022
    Applicant: ETERNAL MATERIALS CO., LTD.
    Inventor: WEI-CHIH CHEN
  • Publication number: 20220122898
    Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.
    Type: Application
    Filed: April 1, 2021
    Publication date: April 21, 2022
    Inventors: Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11282804
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a polymer layer and a redistribution layer. The encapsulant laterally encapsulates the die. The polymer layer is on the encapsulant and the die. The polymer layer includes an extending portion having a bottom surface lower than a top surface of the die. The redistribution layer penetrates through the polymer layer to connect to the die.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20220082884
    Abstract: An electronic device includes: a first substrate; a second substrate opposite to the first substrate; a black matrix layer disposed between the first and second substrates and including a first pixel region and a first shielding region disposed along a first direction, wherein the first pixel region includes a first sub-pixel opening; a scan line disposed between the first and second substrates and extending along a second direction different from the first direction, wherein the first shielding region overlaps the scan line; and a first color resist and a second color resist disposed in the fielding region, having different colors and overlapping each other to form an overlapping region, wherein a width of the overlapping region at the second direction is greater than or equal to 0 and less than 50% of a width of the first sub-pixel opening at the second direction.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Inventors: Wei-Chih CHEN, Chih-Ming LIANG
  • Patent number: 11270927
    Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, an adhesion promoter layer, a RDL structure and a conductive terminal. The TIV is laterally aside the die. The encapsulant laterally encapsulates the die and the TIV. The adhesion promoter layer is sandwiched between the TIV and the encapsulant. The RDL structure is electrically connected to the die and the TIV. The conductive terminal is electrically connected to the die through the RDL structure.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
  • Publication number: 20220068746
    Abstract: A package structure includes a semiconductor die, an insulating encapsulation, a first redistribution circuit structure and a surface-modifying film. The semiconductor die has conductive terminals. The insulating encapsulation laterally encapsulates the semiconductor die and exposes the conductive terminals. The first redistribution circuit structure is located over the insulating encapsulation and electrically connected to the semiconductor die. The surface-modifying film is located on the insulating encapsulation and has a plurality of openings exposing edges of the conductive terminals, wherein the surface-modifying film separates the first redistribution circuit structure from the insulating encapsulation.
    Type: Application
    Filed: August 30, 2020
    Publication date: March 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • Publication number: 20220051978
    Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
  • Publication number: 20220034956
    Abstract: A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.
    Type: Application
    Filed: June 3, 2021
    Publication date: February 3, 2022
    Inventors: WEI-CHIH CHEN, BEN-MOU YU, YI-YEN LIN
  • Publication number: 20220020986
    Abstract: An electrode material of a lithium-ion battery is provided. The electrode material of the lithium-ion battery has 5 to 70 parts by weight of unbuffered active material; and 30 to 95 parts by weight of buffered active material. By adding a specific proportion of a buffered material (such as the graphite material particles), the electrode material of the lithium-ion battery avoids or reduces breakage or cracking of the unbuffered active material themselves or the shell thereof during a rolling step, so a cycle life of a battery can be improved.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 20, 2022
    Inventors: Po-chin CHEN, Wei-chih CHEN, Yi-hsun CHEN, Hsiang-yu HSU, Kai-Chih HSU, Yuan-ping YANG
  • Patent number: 11223759
    Abstract: An exposure method and an image sensing device using the same are provided. The exposure method includes the following steps: obtaining a first light-intensity confidence value of each pixel unit based on a first exposure time; obtaining a second light-intensity confidence value of each pixel unit based on a second exposure time, wherein the second light-intensity confidence value is different from the first light-intensity confidence value; and taking the phase difference value, corresponding to one of the light-intensity confidence value and the second light-intensity confidence value of each pixel unit, as an output value of the corresponding pixel unit.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 11, 2022
    Inventors: Shou-Te Wei, Wei-Chih Chen, Jun-Hao Wu
  • Patent number: 11201079
    Abstract: A wafer chuck includes a chuck body and a plurality of seal rings. The chuck body includes a carrying surface configured to receive a wafer and at least one vacuum hole disposed on the carrying surface. A ratio of a diameter of the carrying surface to a diameter of the wafer is substantially equal to greater than 45% and substantially equal to or smaller than 90%. The seal rings are disposed on the carrying surface and configured to physically contact with the wafer. The seal rings surround the vacuum hole.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sih-Hao Liao, Chen-Hua Yu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
  • Publication number: 20210375762
    Abstract: A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.
    Type: Application
    Filed: March 9, 2021
    Publication date: December 2, 2021
    Inventors: Chung-Hui CHEN, Cheng-Hsiang HSIEH, Wan-Te CHEN, Tzu Ching CHANG, Wei Chih CHEN, Ruey-Bin SHEEN, Chin-Ming FU