Patents by Inventor Wei-Chih Chien
Wei-Chih Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107495Abstract: During operation, a computer system may provide instructions to access points in an indoor environment to measure relative distances between the access points. Then, the computer system may receive the measured relative distances. Moreover, the computer system may calculate geographic locations of the access points based at least in part on the measured relative distances. Next, the computer system may select potential anchor access points in the access points, and may provide, to an electronic device, information specifying the potential anchor access points. Furthermore, the computer system may receive, from the electronic device, second information specifying anchor access points in the potential access points and defined locations of the anchor access points. Additionally, the computer system may update the geographic locations based at least in part on the defined of the anchor access points, and may provide, to the access points, the updated geographic locations.Type: ApplicationFiled: September 19, 2023Publication date: March 28, 2024Applicant: ARRIS Enterprises LLCInventors: See Ho Ting, Cheng-Ming Chien, Kuan-Chih Chou, Lin Zeng, Chih-Ming Lam, Wei Xiang Ng, Arsalan Habib, Anand Krishnamachari
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Patent number: 11869613Abstract: A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.Type: GrantFiled: January 13, 2022Date of Patent: January 9, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Chih Chien, Hsiang-Lan Lung
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Publication number: 20230130293Abstract: A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.Type: ApplicationFiled: January 13, 2022Publication date: April 27, 2023Inventors: Wei-Chih CHIEN, Hsiang-Lan LUNG
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Patent number: 11590620Abstract: The present application discloses a motion control method for dual-spindle machining and a dual-spindle machine apparatus. A control device performs data reconstruction of segmentation and checkpoint setting according to first and second data, respectively, to correspondingly form first and second instruction sequences, thereby simultaneously controlling two motion control cards, allowing two machining devices coupled at a back end of the motion control cards to perform machining on two opposite sides of a workpiece. With the checkpoints arranged in the instruction sequences, the machining devices each having one machining tool are provided with a collaboration mechanism, so that the control device is allowed to continue sending instructions of the next segment to the two motion control cards upon arrival of both the instruction sequences at the checkpoints.Type: GrantFiled: January 4, 2022Date of Patent: February 28, 2023Assignee: RENYI MEDICAL CO., LTD.Inventors: Wei-Chih Chien, Meng-Long Lai
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Patent number: 11557342Abstract: A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.Type: GrantFiled: August 17, 2021Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: Nanbo Gong, Wei-Chih Chien, Matthew Joseph BrightSky, Christopher P. Miller, Hsiang-Lan Lung
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Publication number: 20220407000Abstract: A memory cell formed in a pillar structure between a first electrode and a second electrode includes laminated encapsulation structure. In one example, the pillar includes a body of ovonic threshold switch material, carbon-based intermediate layers, metal layers and a body of phase change memory material in electrical series between the first and second electrodes. The laminated encapsulation structure surrounds the pillar. The laminated dielectric encapsulation structure comprises at least three conformal layers, including a first layer of material, a second conformal layer of a second layer material different from the first layer material; and a third conformal layer of a third layer material different from the second layer material.Type: ApplicationFiled: June 16, 2021Publication date: December 22, 2022Applicants: MACRONIX INTERNATIONAL CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Hsiang YANG, Hsiang-Lan LUNG, Wei-Chih CHIEN, Cheng-Wei CHENG, Matthew J. BRIGHTSKY
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Publication number: 20220219274Abstract: The present application discloses a motion control method for dual-spindle machining and a dual-spindle machine apparatus. A control device performs data reconstruction of segmentation and checkpoint setting according to first and second data, respectively, to correspondingly form first and second instruction sequences, thereby simultaneously controlling two motion control cards, allowing two machining devices coupled at a back end of the motion control cards to perform machining on two opposite sides of a workpiece. With the checkpoints arranged in the instruction sequences, the machining devices each having one machining tool are provided with a collaboration mechanism, so that the control device is allowed to continue sending instructions of the next segment to the two motion control cards upon arrival of both the instruction sequences at the checkpoints.Type: ApplicationFiled: January 4, 2022Publication date: July 14, 2022Inventors: WEI-CHIH CHIEN, MENG-LONG LAI
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Publication number: 20210375360Abstract: A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.Type: ApplicationFiled: August 17, 2021Publication date: December 2, 2021Inventors: Nanbo Gong, Wei-Chih Chien, Matthew Joseph BrightSky, Christopher P. Miller, Hsiang-Lan Lung
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Patent number: 11139025Abstract: A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.Type: GrantFiled: January 22, 2020Date of Patent: October 5, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, MACRONIX INTERNATIONAL CO., LTDInventors: Nanbo Gong, Wei-Chih Chien, Matthew Joseph BrightSky, Christopher P. Miller, Hsiang-Lan Lung
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Publication number: 20210249600Abstract: A memory element comprises a carbon deposit, such as a carbon buffer layer, on a body of phase change memory material, disposed between first and second electrodes. A carbon deposit is found to improve endurance of phase change memory cells by five orders of magnitude or more. Examples include “mushroom” style memory elements, as well as other types including 3D arrays of cross-point elements.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Chih CHIEN, Hsiang-Lan LUNG
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Publication number: 20210225441Abstract: A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.Type: ApplicationFiled: January 22, 2020Publication date: July 22, 2021Inventors: Nanbo Gong, Wei-Chih Chien, Matthew Joseph BrightSky, Christopher P. Miller, Hsiang-Lan Lung
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Publication number: 20210035644Abstract: A memory apparatus and a data access method for a memory are provided. The data access method includes: receiving a data erase command for performing a data erase operation; and, during the data erase operation: configuring a selected memory cell block in the memory according to the data erase command; providing a flag memory cell corresponding to the selected memory cell block, erasing a data in the flag memory cell according to the data erase command, and keeping a data in a plurality of selected memory cells in the selected memory cell block unchanged.Type: ApplicationFiled: August 1, 2019Publication date: February 4, 2021Applicant: Macronix International Co., Ltd.Inventors: WEI-CHIH CHIEN, Hsin-Yi Ho, Hsiang-Lan Lung
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Patent number: 10312276Abstract: An image sensor package, comprising a silicon substrate; an image sensor pixel array that is formed on the silicon substrate; a peripheral circuit region that is formed around the image sensor pixel array on the silicon substrate; a redistribution layer (RDL) that is electrically coupled to the peripheral circuit region; at least one solder ball that is electrically coupled to the RDL; and a cover glass that is coupled to the RDL. No part of the RDL is located directly above or below the image sensor pixel array. No part of the at least one solder ball is located directly above or below the silicon substrate. A dark material layer is implemented to prevent an edge flare effect of the image sensor pixel array.Type: GrantFiled: August 2, 2017Date of Patent: June 4, 2019Assignee: OmniVision Technologies, Inc.Inventors: Wei-Chih Chien, Wei-Feng Lin
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Publication number: 20190043904Abstract: An image sensor package, comprising a silicon substrate; an image sensor pixel array that is formed on the silicon substrate; a peripheral circuit region that is formed around the image sensor pixel array on the silicon substrate; a redistribution layer (RDL) that is electrically coupled to the peripheral circuit region; at least one solder ball that is electrically coupled to the RDL; and a cover glass that is coupled to the RDL. No part of the RDL is located directly above or below the image sensor pixel array. No part of the at least one solder ball is located directly above or below the silicon substrate. A dark material layer is implemented to prevent an edge flare effect of the image sensor pixel array.Type: ApplicationFiled: August 2, 2017Publication date: February 7, 2019Inventors: Wei-Chih Chien, Wei-Feng Lin
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Patent number: 10157671Abstract: An integrated circuit includes a memory array including a plurality of memory cells disposed at respective cross points of a plurality of first access lines and a plurality of second access lines. A selected memory cell has a first threshold voltage Vth(S) of set state and a second threshold voltage Vth(R) of reset state. Control circuitry is configured to apply a write voltage Vw to the selected first access line during a write operation, to apply a read voltage Vr to the selected first access line during a read operation, and to apply a same inhibit voltage Vu to unselected first and second access lines during the write and read operations, where ½Vw>Vu>Vw?Vth(S).Type: GrantFiled: September 12, 2017Date of Patent: December 18, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsiang-Lan Lung, Wei-Chih Chien
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Patent number: 10020335Abstract: A short-resistant CSP includes an isolation layer, an electrically conductive RDL, and an insulating layer. The electrically conductive RDL is on the isolation layer and includes a first and a second RDL segment. The insulating layer includes a first insulator portion between the isolation layer and the first RDL segment to improve electrical isolation between the first and second RDL segments. A method for preventing short-circuiting between conductors of CSP includes (1) depositing a first insulating layer on a first substrate region, (2) depositing a RDL segment on the substrate above the first substrate region, at least a portion of the first insulating layer being between the first RDL segment and the first substrate region, and (3) depositing a second RDL segment on the substrate above a second substrate region, such that the first insulating layer interrupts a leakage current path between the first and second RDL segments.Type: GrantFiled: September 9, 2016Date of Patent: July 10, 2018Assignee: OmniVision Technologies, Inc.Inventors: Wei-Chih Chien, Ying-Chih Kuo
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Publication number: 20180076248Abstract: A short-resistant CSP includes an isolation layer, an electrically conductive RDL, and an insulating layer. The electrically conductive RDL is on the isolation layer and includes a first and a second RDL segment. The insulating layer includes a first insulator portion between the isolation layer and the first RDL segment to improve electrical isolation between the first and second RDL segments. A method for preventing short-circuiting between conductors of CSP includes (1) depositing a first insulating layer on a first substrate region, (2) depositing a RDL segment on the substrate above the first substrate region, at least a portion of the first insulating layer being between the first RDL segment and the first substrate region, and (3) depositing a second RDL segment on the substrate above a second substrate region, such that the first insulating layer interrupts a leakage current path between the first and second RDL segments.Type: ApplicationFiled: September 9, 2016Publication date: March 15, 2018Inventors: Wei-Chih Chien, Ying-Chih Kuo
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Patent number: 9882126Abstract: A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.Type: GrantFiled: April 9, 2016Date of Patent: January 30, 2018Assignees: International Business Machines Corporation, Macronix International Co. LtdInventors: Matthew J. BrightSky, Huai-Yu Cheng, Wei-Chih Chien, Sangbum Kim, Chiao-Wen Yeh
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Publication number: 20170294578Abstract: A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.Type: ApplicationFiled: April 9, 2016Publication date: October 12, 2017Applicants: International Business Machines Corporation, Macronix International Co., LtdInventors: Matthew J. BrightSky, Huai-Yu Cheng, Wei-Chih Chien, Sangbum Kim, Chiao-Wen Yeh
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Patent number: 9680095Abstract: A structure for a resistive memory device and a method to fabricate the same is disclosed. The method includes providing a bottom electrode comprising a metal and forming a memory layer on the bottom electrode. The memory layer includes a first layer of metal oxide, and a second layer including the nitrogen-containing metal oxide. A top electrode is formed over the memory layer.Type: GrantFiled: June 28, 2013Date of Patent: June 13, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: I Yueh Chen, Wei-Chih Chien