Abstract: A structure for a resistive memory device and a method to fabricate the same is disclosed. The method includes providing a bottom electrode comprising a metal and forming a memory layer on the bottom electrode. The memory layer includes a first layer of metal oxide, and a second layer including the nitrogen-containing metal oxide. A top electrode is formed over the memory layer.

Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.

Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.

Abstract: A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.

Abstract: An operation method for a memory device is disclosed. An operation state of the memory device is determined. If to be operated in a first operation state, the memory device is applied by a reset pulse. If to be operated in a second operation state, the memory device is applied by the reset pulse and at least a first incremental pulse set verification current, and an allowable maximum current of the first incremental pulse set verification current is lower than a melt current. If to be operated in a third operation state, the memory device is applied by the reset pulse and at least a first identical pulse set verification current, and an allowable maximum current of the first identical pulse set verification current is lower than the melt current. If to be operated in a fourth operation state, the memory device is applied by a set pulse.

Abstract: A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a N+ type semiconductor material or a P+ type semiconductor material, and the memory and the top electrode produce a self-rectified property.

Abstract: A resistive memory and a fabricating method thereof are provided. The resistive memory includes first and second electrodes, a variable resistance material layer, a first dielectric layer, and a second dielectric layer. The first electrode includes a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer includes a sidewall and first and second surfaces opposite to each other, wherein the first surface is connected with the first portion of the first electrode and the second surface is electrically connected with the second electrode. The second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion. The first dielectric layer is disposed between the first and the second electrodes. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode.

Abstract: A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.

Abstract: A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.

Abstract: A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance. A resistive memory array including an array of the above resistive memory units, word lines and bit lines is also described, wherein the word (bit) lines are coupled to the first (second) memory layers.

Abstract: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

Abstract: A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.

Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.

Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.

Abstract: A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.

Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.

Abstract: A structure for a resistive memory device and a method to fabricate the same is disclosed. The method includes providing a bottom electrode comprising a metal and forming a memory layer on the bottom electrode. The memory layer includes a first layer of metal oxide, and a second layer including the nitrogen-containing metal oxide. A top electrode is formed over the memory layer.

Abstract: A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a N+ type semiconductor material or a P+ type semiconductor material, and the memory and the top electrode produce a self-rectified property.

Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.

Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.