Abstract: A method for designing an integrated circuit comprises identifying a first circuit component that presents a voltage (IR) drop being equal to or greater than an IR drop threshold through at least an IR drop analysis, splitting the plurality of timing paths into a first subset of timing paths and a second subset of timing paths, based on a timing margin threshold; and adding a second circuit component disposed along the second subset of timing paths, while keeping the first circuit component disposed along the first subset of timing paths. The first circuit component can be disposed along a plurality of timing paths that each extend from a first storage node and to a second storage node and can be each associated with a timing margin.

Abstract: A method (of manufacturing a semiconductor device, a corresponding layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction) includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information; and, for each cell in the subset of the cells, the generating a sidefile including: populating the sidefile with a first neighbor-specific proximity-effect (NSPE) parameter (corresponding to an inter-cell proximity-effect induced by the first neighbor cell) identifying a nearest first transistor of the first neighbor cell; and populating the sidefile with a second NSPE parameter (corresponding to an inter-cell proximity-effect induced by the second neighbor cell) identifying a nearest first transistor of the second neighbor cell.

Abstract: For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information.

Abstract: A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.

Abstract: A method (of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells) includes generating a netlist which represents the subset, the generating a netlist including: In some embodiments, for each TWEI cell represented in the netlist, and for a given transistor in a given well in a given cell, expanding the netlist to include one or more proximity-effect-inducer (PEI) parameters, each PEI parameter being related to an intra-cell physical proximity of the given transistor to an edge of the given well (given well-edge).

Abstract: For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information.

Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.

Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.

Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.

Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.

Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to generate a first output signal based on a logic value of a first input signal. The output stage is configured to receive the first output signal transmitted according to the logic value of the first input signal, and to generate a second output signal. The second output signal has a logic value that is different from a logic value of the first output signal, and the second output signal and the first input signal has a same logic value.

Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to generate a first output signal based on a logic value of a first input signal. The output stage is configured to receive the first output signal transmitted according to the logic value of the first input signal, and to generate a second output signal. The second output signal has a logic value that is different from a logic value of the first output signal, and the second output signal and the first input signal has a same logic value.

Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.

Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.

Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.

Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.

Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The output stage is configured to adjust a voltage swing of a selected one of the first output signal and the second output signal.

Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The output stage is configured to adjust a voltage swing of a selected one of the first output signal and the second output signal.

Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The selector configured to selectively transmit one of the first output signal and the second output signal according to the first input signal.

Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The selector configured to selectively transmit one of the first output signal and the second output signal according to the first input signal.