Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to a plurality of least significant bits of an input signal. The second DAC circuit is configured to output a second signal according to a plurality of most significant bits of the input signal. A first turn-on time of at least one current source circuit in the first DAC circuit is configured to set the first signal.

Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to a plurality of least significant bits of an input signal. The second DAC circuit is configured to output a second signal according to a plurality of most significant bits of the input signal. A first turn-on time of at least one current source circuit in the first DAC circuit is configured to set the first signal.

Abstract: A semiconductor structure for improving the gate metal adhesion and the Schottky stability, comprising: a III-nitride semiconductor having a top surface on which a conductive area and a non-conductive area are defined; a source contact metal and a first drain contact metal forming ohmic contact with the III-nitride semiconductor on the conductive area, and the first drain contact metal provided at one side of the source contact metal; and a gate metal layer comprising a gate connection line and a first gate finger extending from the gate connection line, the first gate finger interposing between the source contact metal and the first drain contact metal and forming a Schottky contact with the III-nitride semiconductor on the conductive area, wherein the first gate finger has a first terminal anchor at an end thereof surrounding the source contact metal, and the first terminal anchor has an increased width.

Abstract: A method to produce high electron mobility transistors with Boron implanted isolation comprises the following steps: on a substrate forming in sequence a nucleation layer, a buffer layer, a barrier layer and a cap layer; coating a photoresist layer on the cap layer; photomasking and by exposure eliminating the photoresist layer of at least one isolation region; executing plural times an ion implantation process including: adjusting an incident angle of a Boron ion beam with respect to the substrate, and implanting the Boron ion beam into the cap layer, the barrier layer, the buffer layer, the nucleation layer and the substrate within the at least one isolation region so as to form an isolation structure while rotating the substrate by a rotation angle; eliminating the rest of the photoresist layer by exposure; and forming a source, a drain and a gate on the cap layer.

Abstract: A soft-start circuit and a method thereof are described. The circuit includes an amplifier and a voltage ramp generator. The amplifier has a first input end, a second input end, an output end, and a power source control end. The first input end is coupled to a reference voltage. The second input end is coupled to a feedback voltage. The output end outputs an output voltage, and the feedback voltage corresponds to the output voltage. The voltage ramp generator is coupled to the power source control end, and generates a ramp-up voltage. When the ramp-up voltage is lower than a threshold value, the output voltage rises with the ramp-up voltage. When the ramp-up voltage is not lower than the threshold voltage, the output voltage remains at a stable value. A surge current occurring during smooth soft-start or even in operation is thus prevented.

Abstract: A signal generating apparatus comprises an amplifier, which comprises differential input terminals for receiving a first input signal, a common mode output signal adjusting terminal for receiving a second input signal, and an output terminal. The signal generating apparatus may provide two or more differential output signals according to the first input signal, and provide two or more common mode output signals according to the second input signal. The amplifier provides an output signal comprising one of the differential output signals and one of the common mode output signals at the output terminal.

Abstract: A signal generating apparatus comprises an amplifier, which comprises differential input terminals for receiving a first input signal, a common mode output signal adjusting terminal for receiving a second input signal, and an output terminal. The signal generating apparatus may provide two or more differential output signals according to the first input signal, and provide two or more common mode output signals according to the second input signal. The amplifier provides an output signal comprising one of the differential output signals and one of the common mode output signals at the output terminal.

Abstract: A soft-start device including a current source, a first transistor, and a second transistor is described. The first transistor is coupled to the current source, and an amount of current conducted by the first transistor is determined according to a voltage. The second transistor is also coupled to the current source, and an amount of current conducted by the second transistor is determined according to a fixed bias. An initial voltage value of the voltage is smaller than a voltage value of the fixed bias. However, after a soft start, the voltage value of the first voltage is increased gradually to be larger than the voltage value of the fixed bias, such that the soft start may be implemented smoothly.

Abstract: A soft-start device including a current source, a first transistor, and a second transistor is described. The first transistor is coupled to the current source, and an amount of current conducted by the first transistor is determined according to a voltage. The second transistor is also coupled to the current source, and an amount of current conducted by the second transistor is determined according to a fixed bias. An initial voltage value of the voltage is smaller than a voltage value of the fixed bias. However, after a soft start, the voltage value of the first voltage is increased gradually to be larger than the voltage value of the fixed bias, such that the soft start may be implemented smoothly.

Abstract: A soft-start circuit and a method thereof are described. The circuit includes an amplifier and a voltage ramp generator. The amplifier has a first input end, a second input end, an output end, and a power source control end. The first input end is coupled to a reference voltage. The second input end is coupled to a feedback voltage. The output end outputs an output voltage, and the feedback voltage corresponds to the output voltage. The voltage ramp generator is coupled to the power source control end, and generates a ramp-up voltage. When the ramp-up voltage is lower than a threshold value, the output voltage rises with the ramp-up voltage. When the ramp-up voltage is not lower than the threshold voltage, the output voltage remains at a stable value. A surge current occurring during smooth soft-start or even in operation is thus prevented.

Abstract: The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.

Abstract: The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.

Abstract: An InP/InGaAlAs heterojunction bipolar transistor with the characteristics of amplification and negative-differential-resistance phenomenon is presented in the invention. The 3-terminal current-voltage characteristics of the heterojunction bipolar transistor can be controlled by the applied base current. In the large collector current regime, the heterojunction bipolar transistor has the characteristics as similar to conventional bipolar junction transistors. However, in a small collector current regime, both the transistor active region and negative-differential-resistance loci are observed. The negative-differential-resistance phenomenon is caused by the insertion of a thin base layer and a &dgr;-doped sheet. Moreover, the use of a setback layer with a thickness of 50 Å added at the emitter-base junction can suppress the diffusion of doping impurity in the base and reduce the potential spike at emitter-base heterojunction so as to improve the confinement of holes injected from base to emitter.