Patents by Inventor Wei-Chuan Chen

Wei-Chuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456411
    Abstract: A method for fabricating a magnetic tunneling junction (MTJ) element is disclosed. A substrate is provided. A reference layer is formed on the substrate. A tunnel barrier layer is formed on the reference layer. A free layer is formed on the tunnel barrier layer. A composite capping layer is formed on the free layer. The composite capping layer comprises an amorphous layer, a light-element sink layer, and/or a diffusion-stop layer. The reference layer, the tunnel barrier layer, the free layer, and the composite capping layer constitute an MTJ stack.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: September 27, 2022
    Assignee: HeFeChip Corporation Limited
    Inventors: Qinli Ma, Wei-Chuan Chen, Youngsuk Choi, Shu-Jen Han
  • Patent number: 11450564
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Yen-Tsai Yi, Li-Han Chen, Hsiang-Wen Ke
  • Publication number: 20220229500
    Abstract: A control method is provided, applied to an electronic device. The electronic device includes a screen and a knob module. The control method includes: receiving a trigger signal to enable the knob module, and displaying an operating interface corresponding to the knob module on the screen according to the trigger signal, where the operating interface includes a plurality of functional regions that is arranged annularly, and the functional regions are configured to display a plurality of function options, where one of the functional regions shows a marked state; switching the functional region corresponding to the marked state according to a first input signal from the knob module; and selecting the functional region corresponding to the marked state according to a second input signal from the knob module.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 21, 2022
    Inventors: Mu-Chern FONG, Wei-Chuan CHEN, Chi-Rong HSU, Po-Nien CHEN, Lan-Hua HUANG, Wen Hui HUANG, Chi-Ming HUANG, Zhong Wei HONG, Siao-Yun YANG, Hsiao Fan CHEN, Hsiu-Yu KAO
  • Patent number: 11391685
    Abstract: A sensitive device includes a plurality of first conductive nanostructures, a conductive layer and at least one electrode. The conductive layer covers the first conductive nanostructures. An intrinsic melting point of the conductive layer is higher than that of the first conductive nanostructures. At least one of the conductive layer and the first conductive nanostructures is sensitive to gas. The electrode is electrically connected to at least one of the first conductive nanostructures and the conductive layer.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 19, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Po-Yi Chang, Hung-Chuan Liu, Yi-Ting Chou, Wei-Tsung Chen
  • Patent number: 11342496
    Abstract: A semiconductor memory structure includes a substrate, a magnetic tunneling junction (MTJ) stack disposed on the substrate, and an encapsulation layer surrounding the MTJ stack. The encapsulation layer comprises an outer silicon oxynitride layer with a composition of SiOx1Ny1 and an inner silicon oxynitride layer with a composition of SiOx2Ny2, wherein x1/y1>x2/y2.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 24, 2022
    Assignee: HeFeChip Corporation Limited
    Inventors: Hong-Hui Hsu, Wei-Chuan Chen, Qinli Ma, Shu-Jen Han
  • Publication number: 20210343930
    Abstract: A semiconductor memory structure includes a substrate, a magnetic tunneling junction (MTJ) stack disposed on the substrate, and an encapsulation layer surrounding the MTJ stack. The encapsulation layer comprises an outer silicon oxynitride layer with a composition of SiOx1Ny1 and an inner silicon oxynitride layer with a composition of SiOx2Ny2, wherein x1/y1>x2/y2.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Inventors: Hong-Hui Hsu, Wei-Chuan Chen, Qinli Ma, Shu-Jen Han
  • Publication number: 20210328135
    Abstract: A storage layer of a magnetic tunnel junction (MTJ) element is disclosed. The storage layer having perpendicular magnetic anisotropy includes a first ferromagnetic layer, a first dust layer disposed directly on the first ferromagnetic layer, a second ferromagnetic layer disposed directly on the first dust layer, a second dust layer disposed directly on the second ferromagnetic layer, and a third ferromagnetic layer disposed directly on the second dust layer. A material of the first dust layer is different from a material of the second dust layer.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 21, 2021
    Inventors: Qinli Ma, Wei-Chuan Chen, Shu-Jen Han
  • Publication number: 20210265561
    Abstract: A magnetic tunneling junction (MTJ) element includes a reference layer, a tunnel barrier layer on the reference layer, a free layer on the tunnel barrier layer, and a composite capping layer on the free layer. The composite capping layer comprises a diffusion-stop layer on the free layer, a light-element sink layer on the diffusion-stop layer, and an amorphous layer on the light-element sink layer.
    Type: Application
    Filed: May 9, 2021
    Publication date: August 26, 2021
    Inventors: Qinli Ma, Wei-Chuan Chen, Youngsuk Choi, Shu-Jen Han
  • Publication number: 20210020215
    Abstract: A magnetic tunneling junction (MTJ) element is disclosed. The MTJ element includes a reference layer, a tunnel barrier layer on the reference layer, a free layer on the tunnel barrier layer, and a composite capping layer on the free layer. The composite capping layer includes an amorphous layer, a light-element sink layer, and/or a diffusion-stop layer. The composite capping layer is in direct contact with the free layer and forms a first interface with the free layer. The composite capping layer is in direct contact with a top electrode and forms a second interface with the top electrode.
    Type: Application
    Filed: July 21, 2019
    Publication date: January 21, 2021
    Inventors: Qinli Ma, Wei-Chuan Chen, Youngsuk Choi, Shu-Jen Han
  • Publication number: 20210005809
    Abstract: A method for fabricating a magnetic tunneling junction (MTJ) element is disclosed. A substrate is provided. A reference layer is formed on the substrate. A tunnel barrier layer is formed on the reference layer. A free layer is formed on the tunnel barrier layer. A composite capping layer is formed on the free layer. The composite capping layer comprises an amorphous layer, a light-element sink layer, and/or a diffusion-stop layer. The reference layer, the tunnel barrier layer, the free layer, and the composite capping layer constitute an MTJ stack.
    Type: Application
    Filed: September 18, 2019
    Publication date: January 7, 2021
    Inventors: Qinli Ma, Wei-Chuan Chen, Youngsuk Choi, Shu-Jen Han
  • Patent number: 10869725
    Abstract: A simulated method and system for surgical instrument based on tomography are provided. The method includes obtaining a biological stereoscopic image and inputting a parameter set of an implant to be implanted, denoting a target position and an initial position in the biological stereoscopic image, estimating a dimensional coordinate of a contact area of the implant and a living organism when the implant has been implanted into the living organism based on the parameter set, the target position and the initial position in the biological stereoscopic image, and obtaining a physiological data set by re-sampling corresponding to the dimensional coordinate of the implant in the living organism for evaluating the effect after the implant has been implanted into the living organism. Surgeons may evaluate the effect after implantation of implant into the living organism by using the simulated method, enhancing the overall quality and result of the surgery.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: December 22, 2020
    Assignees: China Medical University, China Medical University Hospital
    Inventors: Yi-Wen Chen, Cheng-Ting Shih, Wei-Chuan Chen
  • Patent number: 10868238
    Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Xia Li, Wei-Chuan Chen, Seung Hyuk Kang
  • Patent number: 10811068
    Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Xia Li, Wei-Chuan Chen, Wah Nam Hsu, Seung Hyuk Kang
  • Patent number: 10740017
    Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 11, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Wei-Chuan Chen, Sungryul Kim, Adam Edward Newham, Seung Hyuk Kang, Rashid Ahmed Akbar Attar
  • Patent number: 10693432
    Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 23, 2020
    Assignee: QUALCOMMM Incorporated
    Inventors: Nosun Park, Changhan Hobie Yun, Jonghae Kim, Niranjan Sunil Mudakatte, Xiaoju Yu, Wei-Chuan Chen
  • Publication number: 20200119262
    Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.
    Type: Application
    Filed: October 15, 2018
    Publication date: April 16, 2020
    Inventors: Xia LI, Wei-Chuan CHEN, Seung Hyuk KANG
  • Patent number: 10614942
    Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Mario Francisco Velez, Nosun Park, Wei-Chuan Chen, Niranjan Sunil Mudakatte, Xiaoju Yu, Paragkumar Ajaybhai Thadesar, Jonghae Kim
  • Patent number: 10608174
    Abstract: Double-patterned magneto-resistive random access memory (MRAM) for reducing magnetic tunnel junction (MTJ) pitch for increased MRAM bit cell density is disclosed. In one aspect, to fabricate MTJs in an MRAM array with reduced MTJ row pitch, a first patterning process is performed to provide separation areas in an MTJ layer between what will become rows of fabricated MTJs, which facilitates MTJs in a given row sharing a common bottom electrode. This reduces the etch depth and etching time needed to etch the individual MTJs in a subsequent step, can reduce lateral projections of sidewalls of the MTJs, thereby relaxing the pitch between adjacent MTJs, and may allow an initial MTJ hard mask layer to be reduced in height. A subsequent second patterning process is performed to fabricate individual MTJs. Additional separation areas are etched between free layers of adjacent MTJs in a given row to fabricate the individual MTJs.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Wei-Chuan Chen
  • Publication number: 20200091094
    Abstract: A filter including an insulating die having a plurality of MIM (Metal Insulator Metal) capacitors disposed within the die is disclosed. A 2.5D (2.5 Dimensional) inductor disposed within a redistribution layer (RDL) is electrically coupled to at least one of the plurality of MIM capacitors in the die. A 3D (3 Dimensional) inductor is disposed around the die and is electrically coupled to at least one of the plurality of MIM capacitors.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Inventors: Changhan Hobie YUN, Mario Francisco VELEZ, Nosun PARK, Niranjan Sunil MUDAKATTE, Wei-Chuan CHEN, Paragkumar Ajaybhai THADESAR, Christopher POLLOCK, Xiaoju YU, Rongguo ZHOU, Kai LIU, Jonghae KIM
  • Patent number: 10582609
    Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 3, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Jonghae Kim, Xiaoju Yu, Mario Francisco Velez, Wei-Chuan Chen, Niranjan Sunil Mudakatte, Matthew Michael Nowak, Christian Hoffmann, Rodrigo Pacher Fernandes, Manuel Hofer, Peter Bainschab, Edgar Schmidhammer, Stefan Leopold Hatzl