Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

Abstract: Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.

Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

Abstract: An apparatus for removing a photoresist layer from at least one alignment mark of a wafer is provided. The apparatus includes a holder, a solvent dispenser, and a suction unit. The holder is used to support the wafer, wherein the alignment mark is formed in a peripheral region of the wafer. The solvent dispenser is used to spray a solvent onto the photoresist layer on the alignment mark of the wafer to generate a dissolved photoresist layer. The suction unit is used to remove the dissolved photoresist layer and the solvent from the wafer through exhausting.

Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.

Abstract: Dynamically controlling voltage provided to three-dimensional (3D) integrated circuits (ICs) (3DICs) to account for process variations measured across interconnected IC tiers of 3DICs are disclosed herein. In one aspect, a 3DIC process variation measurement circuit (PVMC) is provided to measure process variation. The 3DIC PVMC includes stacked logic PVMCs configured to measure process variations of devices across multiple IC tiers and process variations of vias that interconnect multiple IC tiers. The 3DIC PVMC may include IC tier logic PVMCs configured to measure process variations of devices on corresponding IC tiers. These measured process variations can be used to dynamically control supply voltage provided to the 3DIC such that operation of the 3DIC approaches a desired process corner. Adjusting supply voltage using the 3DIC PVMC takes into account interconnected properties of the 3DIC such that the supply voltage is adjusted to cause the 3DIC to operate in the desired process corner.

Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

Abstract: A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

Abstract: A simulated method and system for surgical instrument based on tomography are provided, in which the method includes obtaining a biological stereoscopic image and inputting a parameter set of an implant to be implanted; denoting a target position and an initial position in the biological stereoscopic image; estimating a dimensional coordinate of a contact area of the implant and a living organism when the implant has been implanted into the living organism based on the parameter set, the target position and the initial position in the biological stereoscopic image; and obtaining a physiological data set by re-sampling corresponding to the dimensional coordinate of the implant in the living organism for evaluating the effect after the implant has been implanted into the living organism. The surgeons may evaluate the effect after implantation of implant into the living organism by using the aforementioned simulated method, thereby enhancing the overall quality and result of the surgery.

Abstract: Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier. A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells.

Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

Abstract: High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells are disclosed. In one aspect, an exemplary MRAM bit cell includes a coupling column interconnecting an access transistor and a magnetic tunnel junction (MTJ) therein. The coupling column is disposed across a plurality of interconnection layers. In one aspect, the coupling column comprises a high aspect ratio via. In another aspect, the high aspect ratio via is connected directly between a drain contact coupled to a drain of the access transistor and to an end electrode of the MTJ such that no interconnection line and/or interconnection island is provided in the coupling column. In certain aspects, the coupling column may be disposed between an interconnection line and an adjacent interconnection line without increasing an existing interconnection line pitch, thus allowing for a reduction in MRAM bit cell pitch.

Abstract: Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of MTJ elements can provide reduced free layer sizing for enhanced MTJ operational margin. In certain aspects, to reduce size of a free layer during fabrication of an MTJ to provide enhanced write and retention symmetry, ion beam etching (IBE) fabrication process is employed to fabricate a free layer smaller than the pinned layer. To avoid asymmetrical footing being fabricated in free layer due to shadow-effect of neighboring MTJs, an ion beam directed at the MTJ is shadow-effect compensated. The angle of incidence of the ion beam directed at the MTJ is varied as the MTJ is rotated to be less steep when another MTJ is in directional line of the ion beam and the MTJ being fabricated. Thus, the free layer is etched more uniformly in the MTJ while avoiding increased etching damage.

Abstract: A semiconductor device may include a magnetoresistive random-access memory (MRAM) trench having a first conductive barrier liner and a second conductive barrier liner. The MRAM trench may land on a hard mask of a magnetic tunnel junction (MTJ) within an MTJ region of the semiconductor device. The semiconductor device may also include a logic trench having the first conductive barrier liner. The semiconductor device may further include a logic via having the first conductive barrier liner. The logic via may land on a first portion of a conductive interconnect (Mx) within a logic region of the semiconductor device.

Abstract: Provided are exemplary circuits including a magnetoresistive random-access memory (MRAM) and methods for fabricating the circuits. In an example, a circuit includes an MRAM. The circuit includes a bottom interconnect in a bottom interconnect level. The bottom interconnect is configured to route a signal outside of a magnetic tunnel junction (MTJ) stack. The circuit includes the MTJ stack formed on a bottom electrode at least partially embedded in the bottom interconnect level. Optionally, the circuit also includes an encapsulation layer encapsulating at least a portion of the MTJ stack. The encapsulation layer is also an electromigration cap for a second bottom interconnect in the bottom interconnect level. The second bottom interconnect is a not part of the MTJ stack. Optionally, the bottom electrode is self-aligned with the bottom interconnect.

Abstract: Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of MTJ elements can provide reduced free layer sizing for enhanced MTJ operational margin. In certain aspects, to reduce size of a free layer during fabrication of an MTJ to provide enhanced write and retention symmetry, ion beam etching (IBE) fabrication process is employed to fabricate a free layer smaller than the pinned layer. To avoid asymmetrical footing being fabricated in free layer due to shadow-effect of neighboring MTJs, an ion beam directed at the MTJ is shadow-effect compensated. The angle of incidence of the ion beam directed at the MTJ is varied as the MTJ is rotated to be less steep when another MTJ is in directional line of the ion beam and the MTJ being fabricated. Thus, the free layer is etched more uniformly in the MTJ while avoiding increased etching damage.

Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers. An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR. The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.

Abstract: A semiconductor device may include a magnetoresistive random-access memory (MRAM) trench having a first conductive barrier liner and a second conductive barrier liner. The MRAM trench may land on a hard mask of a magnetic tunnel junction (MTJ) within an MTJ region of the semiconductor device. The semiconductor device may also include a logic trench having the first conductive barrier liner. The semiconductor device may further include a logic via having the first conductive barrier liner. The logic via may land on a first portion of a conductive interconnect (Mx) within a logic region of the semiconductor device.

Abstract: An MRAM cell may include a magnetic tunneling junction (MTJ). The MTJ includes a pin layer, a barrier layer, a free layer, and a capping layer. The MRAM cell further includes a bidirectional diode selector, directly coupled to an electrode of the MTJ, to enable access to the MTJ.

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a spacer on an exposed side portion of the MTJ device. The method further includes forming an etch-resistant protective coating associated with the MTJ device. The etch-resistant protective coating provides greater etch resistance than the spacer.