Patents by Inventor Wei-Chun Tsai

Wei-Chun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155935
    Abstract: A compound comprising a first ligand LA of Formula I, In Formula I, moiety B is a monocyclic ring or a polycyclic fused ring system; X1, X2, and Z1 are C or N; Y1 is O, S, Se, Te, CRR?, SiRR?, GeRR?, PR, AsR, SbR, or BiR; K1 is a direct bond, O, S, N(R?), P(R?), B(R?), C(R?)(R?), or Si(R?)(R?); each R, R?, R?, R?, RA, and RB is hydrogen or a general substituent; any two substituents may be joined or fused to form a ring; LA is coordinated to a metal M to form a 5-membered or 6-membered chelate ring; and two RB substituents join to form a 5-membered ring if Y1 is O, S, or Se. Formulations, OLEDs, and consumer products comprising the compound are also provided.
    Type: Application
    Filed: September 20, 2023
    Publication date: May 9, 2024
    Applicant: Universal Display Corporation
    Inventors: Wei-Chun SHIH, Harvey WENDT, Jui-Yi TSAI, Pierre-Luc T. BOUDREAULT, Alexey Borisovich DYATKIN
  • Publication number: 20240140973
    Abstract: A compound comprising a ligand of LA of Formula I, is provided with variables as defined herein. Formulations, OLEDs, and consumer products including the compound are also disclosed.
    Type: Application
    Filed: December 13, 2023
    Publication date: May 2, 2024
    Applicant: Universal Display Corporation
    Inventors: Jui-Yi TSAI, Alexey Borisovich DYATKIN, Walter YEAGER, Pierre-Luc T. BOUDREAULT, Wei-Chun SHIH, Eric A. MARGULIES
  • Patent number: 11970508
    Abstract: Provided are transition metal compounds having 1,2,3-triazine. Also provided are formulations comprising these transition metal compounds having 1,2,3-triazine. Further provided are OLEDs and related consumer products that utilize these transition metal compounds having 1,2,3-triazine.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: April 30, 2024
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Zhiqiang Ji, Pierre-Luc T. Boudreault, Wei-Chun Shih, Alexey Borisovich Dyatkin, Jui-Yi Tsai
  • Publication number: 20240130220
    Abstract: Provided are organometallic compounds comprising iridium as a central metal atom which is coordinated by two three-dentate ligands which each comprise at least three 5-membered or 6-membered rings. Also provided are formulations comprising these organometallic compounds. Further provided are organic light emitting devices (OLEDs) and related consumer products that utilize these organometallic compounds.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 18, 2024
    Applicant: UNIVERSAL DISPLAY CORPORATION
    Inventors: Jui-Yi TSAI, Walter YEAGER, Henry Carl HERBOL, Harvey WENDT, Wei-Chun SHIH, Alexey Borisovich DYATKIN, Elena SHEINA, Chun LIN
  • Publication number: 20240096865
    Abstract: A semiconductor device, includes a first metal layer, a second metal layer, a drain/source contact and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The drain/source contact extends in the second direction and is connected to the second conductor. The at least one conductive via connects the first conductor and the second conductor through the third conductor.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Wei-Hsin TSAI, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20240090310
    Abstract: A compound comprising a first ligand LA of Formula I, is provided. In Formula I, moiety A is a 5-membered or 6-membered ring; moiety B is a fused ring structure comprising at least four rings; K is a direct bond, O, or S; each of Z1 and Z2 is independently C or N; each RA and RB is independently hydrogen or a General Substituent; at least one RB comprises a cyclic group or an electron-withdrawing group; LA is coordinated to a metal M that has an atomic mass of at least 40 and is optionally coordinated to other ligands; and the ligand LA is optionally linked with other ligands. Formulations, OLEDs, and consumer products including the compound are also provided.
    Type: Application
    Filed: April 10, 2023
    Publication date: March 14, 2024
    Applicant: UNIVERSAL DISPLAY CORPORATION
    Inventors: Jui-Yi TSAI, Alexey Borisovich DYATKIN, Walter YEAGER, Pierre-Luc T. BOUDREAULT, Hsiao-Fan CHEN, Wei-Chun SHIH
  • Publication number: 20240090311
    Abstract: A compound comprising a first ligand LA of Formula I, is provided. In Formula I, K is a direct bond, O, S, N(R?), P(R?), B(R?), C(R?)(R?), or Si(R?)(R?); each of X1 to X8 is C or N; Y is a linking group; each R?, R?, R, R?, R?, R1, RA, RB, and RC is hydrogen or a General Substituent; at least one RC is R*; R* has a structure of Cy-R**, where Cy is a monocyclic ring or a polycyclic fused ring system, which can be further substituted, and R** comprises (i) at least one electron-withdrawing group, (ii) a monocyclic ring or a polycyclic fused ring system, where the monocyclic ring and each ring of the polycyclic fused ring system is independently a 5-membered or 6-membered carbocyclic or heterocyclic ring, or (iii) both (i) and (ii); and LA is coordinated to a metal. Formulations, OLEDs, and consumer products containing the compound are also provided.
    Type: Application
    Filed: April 10, 2023
    Publication date: March 14, 2024
    Applicant: UNIVERSAL DISPLAY CORPORATION
    Inventors: Jui-Yi TSAI, Alexey Borisovich DYATKIN, Tyler FLEETHAM, Wei-Chun SHIH
  • Patent number: 11923251
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 11922844
    Abstract: An integrated driving device is provided. The integrated driving device includes a touch sensing circuit and an optical sensing circuit. The touch sensing circuit is configured to perform touch sensing in a plurality of touch sensing periods during a first frame period. The optical sensing circuit is configured to perform optical sensing during at least one optical sensing period during the first frame period to obtain optical sensing signals for generating first ambient light information. The touch sensing periods and the optical sensing period are non-overlapping. Correspondingly, an operation method of an integrated driving device is also provided.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Wei-Lun Shih, Wu-Wei Lin, Jiun-Jie Tsai, Huang-Chin Tang, Ching-Chun Lin
  • Publication number: 20240074119
    Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.
    Type: Application
    Filed: May 9, 2023
    Publication date: February 29, 2024
    Inventors: Ren-Chun CHANG, Wei-Chih LIN, Sheng-Chi WU, Wen-Yin TSAI, Li-Hsiu CHEN
  • Patent number: 11549946
    Abstract: The present disclosure provides a method for detecting cholangiocarcinoma cells. The capture rate of the cholangiocarcinoma cells of the present disclosure is higher than 70%, and a plurality of octasaccharides with high affinity and specificity can be modified on the surface of magnetic beads to capture and analyze cholangiocarcinoma cells under test, wherein the cholangiocarcinoma cells can be circulating tumor cells in cholangiocarcinoma.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: January 10, 2023
    Assignees: NATIONAL TSING HUA UNIVERSITY, ACADEMIA SINICA
    Inventors: Gwo Bin Lee, Shang-Cheng Hung, Wei-Chun Tsai
  • Patent number: 11450661
    Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsingjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
  • Patent number: 10943995
    Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Publication number: 20210046479
    Abstract: Disclosed herein is an integrated microfluidic chip for detecting cancerous cells, particularly, cholangio-cancerous cells, from a biological sample. Also disclosed herein is a method of detecting cholangio-cancerous cells from a biological sample.
    Type: Application
    Filed: February 27, 2019
    Publication date: February 18, 2021
    Applicants: Academia Sinica, National Tsing Hua University
    Inventors: Shang-Cheng HUNG, Yen-Chun KO, Cheng-Fang TSAI, Gwo-Bin LEE, Wei-Chun TSAI
  • Publication number: 20200355692
    Abstract: The present disclosure provides a method for detecting cholangiocarcinoma cells. The capture rate of the cholangiocarcinoma cells of the present disclosure is higher than 70%, and a plurality of octasaccharides with high affinity and specificity can be modified on the surface of magnetic beads to capture and analyze cholangiocarcinoma cells under test, wherein the cholangiocarcinoma cells can be circulating tumor cells in cholangiocarcinoma.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 12, 2020
    Inventors: Gwo Bin Lee, Shang-Cheng Hung, Wei-Chun Tsai
  • Patent number: 10535573
    Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Publication number: 20190237370
    Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Publication number: 20190123179
    Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).
    Type: Application
    Filed: December 11, 2018
    Publication date: April 25, 2019
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Patent number: 10269666
    Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Patent number: 10164070
    Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai