Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.

Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.

Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: An electronic device is provided. The electronic device includes a substrate, a plurality of electrodes, a soldering material and a plurality of pins. The electrodes are formed in the substrate. The soldering material is disposed on the electrodes. The pins contact the soldering material and electrically connect to the electrodes, wherein at least one of the pins includes a post and a base. The post has a fixing end. The base is disposed on the fixing end of the post, wherein a plurality of openings are formed on the base, passing through the base along an axis, and the axis is parallel to the post.

Abstract: An electronic device is provided. The electronic device includes a substrate, a plurality of electrodes, a soldering material and a plurality of pins. The electrodes are formed in the substrate. The soldering material is disposed on the electrodes. The pins contact the soldering material and electrically connect to the electrodes, wherein at least one of the pins includes a post and a base. The post has a fixing end. The base is disposed on the fixing end of the post, wherein a plurality of openings are formed on the base, passing through the base along an axis, and the axis is parallel to the post.