Patents by Inventor Wei-Chung Hsiao

Wei-Chung Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10939584
    Abstract: The present invention relates to a heat dissipation module and an assembly method thereof. The heat dissipation module includes a heat conductive plate and a buffer member. The heat conductive plate includes a cover section and a first extension section. The cover section covers a heat zone. The buffer member is provided at the heat conductive plate to interferingly match with a housing, so as to conduct heat energy produced by the heat zone to the housing. Accordingly, by configuring the buffer member between the heat conductive plate and the housing, the heat conductive plate is allowed to be reliably thermally adhered to the housing, thereby achieving enhanced heat dissipation efficiency for the heat dissipation module.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 2, 2021
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventors: Hung-Chan Cheng, Wei-Chung Hsiao
  • Publication number: 20210059070
    Abstract: The present invention relates to a heat dissipation module and an assembly method thereof. The heat dissipation module includes a heat conductive plate and a buffer member. The heat conductive plate includes a cover section and a first extension section. The cover section covers a heat zone. The buffer member is provided at the heat conductive plate to interferingly match with a housing, so as to conduct heat energy produced by the heat zone to the housing. Accordingly, by configuring the buffer member between the heat conductive plate and the housing, the heat conductive plate is allowed to be reliably thermally adhered to the housing, thereby achieving enhanced heat dissipation efficiency for the heat dissipation module.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Hung-Chan Cheng, Wei-Chung Hsiao
  • Patent number: 10869007
    Abstract: A management method for an information capturing system includes: detecting communication connections of a plurality of information capturing devices; and when the communication connection of any of the information capturing device is abnormal, generating and outputting a trigger signal to the other of the information capturing devices so as to cause the other of the information capturing devices to execute an information capturing process in response to the trigger signal.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 15, 2020
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Wei-Chung Hsiao
  • Patent number: 10517192
    Abstract: A bendable heat plate is provided. The heat plate includes a housing, a micro-structural layer and a fluid. The housing has an inner surface and an enclosed internal space, and includes a bendable section provided with a channel maintaining structure. The micro-structural layer is formed on the inner surface of the housing. The fluid is filled in the internal space. Using the channel maintaining structure, the bendable section is provided with sufficient space for the fluid to pass through.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 24, 2019
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Wei-Chung Hsiao
  • Patent number: 10462944
    Abstract: A wave absorbing heat dissipation structure adapted to absorb electromagnetic waves of an electronic component and dissipate heat energy of the electronic component. The wave absorbing heat dissipation structure includes a wave absorbing heat dissipation layer and a metal film. The wave absorbing heat dissipation layer is provided at an electronic device, and has a first surface and a second surface opposite to each other, wherein the first surface covers the electronic component. The metal film covers the second surface. The wave absorbing heat dissipation layer is adapted to absorb electromagnetic waves and transmit heat energy. The metal film is adapted to reflect electromagnetic waves and dissipate heat energy. The wave absorbing heat dissipation structure is capable of alleviating interference of electromagnetic waves on an electronic component and enhancing heat dissipation of an electronic component.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 29, 2019
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Wei-Chung Hsiao
  • Publication number: 20190208169
    Abstract: A management method for an information capturing system includes: detecting communication connections of a plurality of information capturing devices; and when the communication connection of any of the information capturing device is abnormal, generating and outputting a trigger signal to the other of the information capturing devices so as to cause the other of the information capturing devices to execute an information capturing process in response to the trigger signal.
    Type: Application
    Filed: September 25, 2018
    Publication date: July 4, 2019
    Inventor: Wei-Chung HSIAO
  • Patent number: 10332567
    Abstract: A heat dissipation and shockproof structure for an electronic module with a hard disk drive is provided. The heat dissipation and shockproof structure includes a carrying component and an elastomer. The carrying component has a fixed segment and two first extending segments. The first extending segments are connected to two ends of the fixed segment, respectively. The fixed segment is connected to a lateral surface of the hard disk drive. The distance between the first extending segments is greater than the thickness of the hard disk drive. The elastomer is disposed partially on the first extending segments at the very least.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 25, 2019
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Wei-Chung Hsiao
  • Publication number: 20190124791
    Abstract: A bendable heat plate is provided. The heat plate includes a housing, a micro-structural layer and a fluid. The housing has an inner surface and an enclosed internal space, and includes a bendable section provided with a channel maintaining structure. The micro-structural layer is formed on the inner surface of the housing. The fluid is filled in the internal space. Using the channel maintaining structure, the bendable section is provided with sufficient space for the fluid to pass through.
    Type: Application
    Filed: March 9, 2018
    Publication date: April 25, 2019
    Inventor: Wei-Chung Hsiao
  • Patent number: 10141266
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10109572
    Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and having a surface exposed from the first surface of the dielectric layer; a plurality of conductive posts embedded in the dielectric layer and electrically connected to the first circuit layer and having one ends exposed from the second surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer and electrically connected the ends of the conductive posts exposed from the second surface of the dielectric layer; and a plurality of protruding elements formed on the surface of the first circuit layer exposed from the first surface of the dielectric layer, thereby providing a large contact area so as to strengthen bonding between a semiconductor chip and the first circuit layer of the package structure.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 23, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Wei-Chung Hsiao
  • Patent number: 10096491
    Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 9, 2018
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Wei-Chung Hsiao, Ming-Chen Sun, Liang-Yi Hung
  • Patent number: 10068842
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 4, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10043757
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Grant
    Filed: May 10, 2015
    Date of Patent: August 7, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10025945
    Abstract: A decryption method for use in displaying data includes the steps of executing a display instruction of an object inclusive of a plurality of data, displaying an unencrypted data, but not an encrypted data, of the data on a display unit according to the display instruction, detecting a trigger signal during the state of displaying the unencrypted data but not displaying the encrypted data, entering a password-receiving state in response to the trigger signal and detecting a password signal during the password-receiving state, determining whether the password signal matches a default password, and displaying the unencrypted data and the encrypted data on the display unit when the password signal matches the default password. Therefore, with the decryption method, no person other than the object owner is aware of the encrypted data.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 17, 2018
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Wei-Chung Hsiao
  • Patent number: 10002825
    Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 19, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9899249
    Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170352615
    Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 7, 2017
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170309537
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170301658
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170287840
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Application
    Filed: June 13, 2017
    Publication date: October 5, 2017
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen