Patents by Inventor Wei Fu

Wei Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250070912
    Abstract: Methods, apparatus, and systems that relate to rate matching scheme design for polar coding, PAC coding, or other pre-transformed polar coding are described. One example method includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by 1) performing a polar transform with H components and 2) performing either no pre-transform or at least two pre-transform operations; wherein the polar transform is based on H polar matrices G(N0), G(N1), . . . , G(NH?1), wherein H, K and E are integers greater than 1, wherein a polar matrix G(Ni) is of size Ni. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.
    Type: Application
    Filed: November 1, 2024
    Publication date: February 27, 2025
    Inventors: Chulong LIANG, Wei ZHAO, Jin XU, Liguang LI, Guanghui YU, Jian KANG, Qiang FU
  • Publication number: 20250072058
    Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a substrate, complex two-dimensional material layers disposed over the substrate, a gate structure and source and drain regions. The complex two-dimensional material layers are arranged spaced apart from one each other and in parallel to one another. The gate structure is disposed across and wraps around and surrounds first portions of the complex two-dimensional material layers. The source and drain regions are disposed on opposite sides of the gate structure and wrap around and surround second portions of the complex two-dimensional material layers.
    Type: Application
    Filed: August 21, 2023
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jer-Fu Wang, Hung-Li Chiang, Goutham Arutchelvan, Wei-Sheng Yun, Chao-Ching Cheng, Iuliana Radu
  • Publication number: 20250071923
    Abstract: A card edge connector includes: a connector base having a card slot and plural terminals; a latch located at one end of the connector base for locking a card; and a releasing member. The releasing member includes two levers and a moving member, the levers are connected with the connector base in a pivoting manner, a first end of the lever is connected with the latch and an opposite second end of the lever is coupled to the moving member, wherein when the card is inserted into the slot and presses against the moving member downwards, the moving member drives the second ends of the levers to move downward, resulting in the first ends moving upwards to push the latch to lock with the card, and when the card is pulled out the moving member resets and drives the levers to release the latch from the card.
    Type: Application
    Filed: August 19, 2024
    Publication date: February 27, 2025
    Inventors: KUO-CHUN HSU, Ming-Yi Gong, Yu-Che Huang, Wen-Lung Hsu, Po-Fu Chen, Xun Wu, Wen-Ting Yu, Chin-Chuan Wu, Wei-Chia Liao
  • Publication number: 20250072174
    Abstract: A light emitting substrate is provided. The light emitting substrate includes light emitting elements of multiple types. The light emitting elements of different types are configured to emit light of a same color but different wavelength ranges. Light emitting elements of a respective type of the light emitting elements of multiple types are substantially evenly distributed in the light emitting substrate.
    Type: Application
    Filed: April 25, 2023
    Publication date: February 27, 2025
    Applicants: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Wei Zhong, Haijun Shi, Changjia Fu, Qingshan Qu, Haiyan Wan
  • Publication number: 20250068423
    Abstract: Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 27, 2025
    Applicant: Intel Corporation
    Inventors: Jorge Eduardo Parra Osorio, Jiasheng Chen, Supratim Pal, Vasanth Ranganathan, Guei-Yuan Lueh, James Valerio, Pradeep Golconda, Brent Schwartz, Fangwen Fu, Sabareesh Ganapathy, Peter Caday, Wei-Yu Chen, Po-Yu Chen, Timothy Bauer, Maxim Kazakov, Stanley Gambarin, Samir Pandya
  • Patent number: 12237577
    Abstract: A cavity-backed slot antenna system provided in this disclosure is installed in a housing of an electronic device and includes a metal cavity, a supporting element, an antenna device, a conductive post, and a coupling metal part. The metal cavity is in the housing and includes an opening and a closed surface opposite to each other. A slot is on the closed surface. The supporting element is in the metal cavity. The antenna device is in the metal cavity and on the supporting element, to expose one side surface of the antenna device. The antenna device includes a feed source. The conductive post penetrates the antenna device and connects to the metal cavity. The coupling metal part is in the housing and close to the opening of the metal cavity, so that the coupling metal part is close to and corresponds to the feed source of the antenna device.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: February 25, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Shih-Hsun Chang, Wei-Lin Tsai, Zhi-Zeng Cheng, You-Fu Cheng, Tsung-Hsun Hsieh
  • Patent number: 12238158
    Abstract: Various embodiments herein provide techniques for Session Description Protocol (SDP)-based signaling of camera calibration parameters for multiple video streams. In embodiments, a device may receive an SDP attribute to indicate that a bitstream included in a real-time transport protocol (RTP)-based media stream includes camera calibration parameters. The device may obtain the camera calibration parameters based on the SDP attribute, and process the RTP-based media stream based on the camera calibration parameters. In embodiments, the camera calibration parameters may be used to stitch together (e.g., align and/or synchronize) the multiple video streams. In embodiments, the stitched video streams may form an immersive video content (e.g., 360-degree video content). Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Ozgur Oyman, Gang Shen, Wenqing Fu, Wei Zong, Juan Zhao
  • Publication number: 20250062350
    Abstract: The present disclosure relates to the field of sodium ion battery technology, in particular, to a cathode material, a preparation method thereof, and a sodium ion battery. The present disclosure relates to a cathode material including a Prussian Blue substrate, and a first coating layer and a second coating layer successively coated on the surface of the Prussian Blue substrate; a material forming the first coating includes a polymer of tannic acid; a material forming the second coating layer includes at least one of hexadecylamine, octadecylamine, octadecyl phosphate, N-phenyl-bis(trifluoromethanesulfonimide), 1H,1H,2H,2H-perfluorodecyl triethoxysilane, and 1H,1H,2H,2H-perfluorodecanethiol. The cathode material of the present disclosure effectively solves the problem of hygroscopicity of Prussian Blue cathode material and effectively improves the storage property and electrochemical performance of the cathode material in air.
    Type: Application
    Filed: March 13, 2024
    Publication date: February 20, 2025
    Inventors: Wuxing ZHANG, Jiayu PENG, Shiqi LIU, Wei FU, Yizhi YAN, Shitao CHEN, Zhibin DENG, Yulin WU
  • Publication number: 20250062086
    Abstract: A keyboard including a key module is provided. The key module includes a keycap, a rigid modular circuit board and a linkage element. The linkage element is located between the keycap and the modular circuit board. The key module is detachably disposed on the keyboard, so that the key module, either in its entirety or as a part, could be disassembled from or assembled to the keyboard.
    Type: Application
    Filed: August 14, 2024
    Publication date: February 20, 2025
    Inventors: Cheng-Kun LIAO, Ming-Fu Yen, Wei-Jung Huang, Cheng-Hsiung Huang, Chun-Chieh Huang
  • Publication number: 20250062779
    Abstract: Methods, apparatus, and systems that relate to rate matching scheme design for polar coding, PAC coding, or other pre-transformed polar coding are disclosed. In one example aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by performing a polar transform with H components and a pre-transform; wherein the polar transform is based on H polar matrices G(N0), G(N1), . . . , G(NH?0), wherein E, K, H are integers greater than 1, wherein a polar matrix G(N0) is of size Ni. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Chulong LIANG, Wei ZHAO, Jin XU, Liguang LI, Guanghui YU, Jian KANG, Qiang FU
  • Patent number: 12229466
    Abstract: An image displaying device includes a planar display panel and a light penetrating unit. The planar display panel displays a plane image. The planar display panel at least includes a first pixel group, a second pixel group and a third pixel group. The second pixel group is located between the first pixel group and the third pixel group. When vision passes through the light penetrating unit toward the planar display panel, the vision acquires a second distance of a second imaging position within the plane image relevant to the second pixel group relative to the planar display panel being greater than a first distance of a first imaging position within the plane image relevant to the first pixel group relative to the planar display panel and a third distance of a third imaging position within the plane image relevant to the third pixel group relative to the planar display panel.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 18, 2025
    Assignee: Qisda Corporation
    Inventors: Hao-Chun Tung, Hsin-Che Hsieh, Wei-Jou Chen, Po-Fu Wu, Yu-Fu Fan, Chih-Ming Chang
  • Patent number: 12229553
    Abstract: A software developer proxy tool accesses microservice applications for a software development project by connecting the developer proxy tool to a common port on a computer network. The tool implements software and hardware to register a plurality of the microservice applications on connection ports that connect to the developer proxy tool at an address for the common port. Data requests among the microservices are handled by the developer proxy tool via the common port. The tool sequentially queries selected microservice applications on the respective connection ports to determine availability for completing a request. The tool receives responses back from microservices and directs the responses back to the requesting program. Failed requests trigger use of remote or third party microservice applications that may be available over an internet connection.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: February 18, 2025
    Assignee: Change Healthcare Holdings, LLC
    Inventors: Henry Spivey, Chun-Fu Chang, Wei-Yuan Lo
  • Publication number: 20250055595
    Abstract: Methods, apparatus, and systems that relate to Polarization-Adjusted Convolutional (PAC) coding with variable lengths are disclosed. In one example aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transform that is applied prior to applying a Polar transform having a size of N. The transform is based on at least one index set that is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers that are less than N and wherein K<N and K<E. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 13, 2025
    Inventors: Chulong LIANG, Jin XU, Wei ZHAO, Liguang LI, Guanghui YU, Jian KANG, Qiang FU
  • Patent number: 12220102
    Abstract: The present disclosure provides an endoscopic image processing method and system, and a computer device. The method can include acquiring a current endoscopic image of a to-be-examined user, and predicting the current endoscopic image by using a deep convolutional network based on a training parameter. The training parameter can be determined according to at least one first endoscopic image and at least one second endoscopic image transformed from the at least one first endoscopic image, where the at least one endoscopic image corresponds to a human body part. The method can further include determining an organ category corresponding to the current endoscopic image. The method provided in the present disclosure can make a prediction process more intelligent and more robust, thereby improving resource utilization of a processing apparatus.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: February 11, 2025
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Xinghui Fu, Zhongqian Sun, Wei Yang
  • Patent number: 12221906
    Abstract: A system for realizing transformation of a thermal power unit based on combined high-parameter and low-parameter molten salts includes a high-parameter molten salt energy storage system, a low-parameter molten salt energy storage system and a thermal power unit. The high-parameter molten salt energy storage system and the low-parameter molten salt energy storage system include an electric heater for heating a molten salt, and an electric energy input end of the electric heater is connected with an electric energy output end of the thermal power unit. The low-parameter molten salt energy storage system includes a low-parameter molten salt heat absorption loop and a low-parameter molten salt heat release loop, and the high-parameter molten salt energy storage system includes a high-parameter molten salt heat absorption loop and a high-parameter molten salt heat release loop.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: February 11, 2025
    Assignee: Xi'an Thermal Power Research Institute Co., L
    Inventors: Xiaohui Song, Wei Han, Kangli Fu, Xu Lu, Haimin Ji, Mingyu Yao, Zaisong Yu, Liang Zhao
  • Patent number: 12224247
    Abstract: A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
    Type: Grant
    Filed: March 26, 2024
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Publication number: 20250046650
    Abstract: A method of wafer bonding includes the following operations. A first surface of the handle wafer, a second surface of the device wafer, or a combination thereof, is coated with water. When the first surface of the handle wafer is coated with water, the handle wafer is rotated at a first rotational speed. When the second surface of the device wafer is coated with water, the device wafer is rotated at a second rotational speed. When the first surface of the handle wafer and the second surface of the device wafer are coated with water, the handle wafer is rotated at a third rotational speed, and the device wafer is rotated at a fourth rotational speed. The first surface of the handle wafer and the second surface of the device wafer are bonded.
    Type: Application
    Filed: November 22, 2023
    Publication date: February 6, 2025
    Inventors: Wei-Jing CHENG, Cheng-Fu FAN
  • Publication number: 20250048541
    Abstract: An electronic device is provided. The electronic device includes a carrier, a first electronic component, a second electronic component, and an encapsulant. The first electronic component is disposed at a first side of the carrier. The second electronic component is disposed at a second side of the carrier opposite to the first side. The encapsulant encapsulates the first electronic component and has an uneven thickness. The encapsulant is configured to reduce a warpage of the carrier.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Jhen CIOU, Jenchun CHEN, Chang-Fu LU, Pai-Sheng SHIH
  • Publication number: 20250048721
    Abstract: Described examples include an integrated circuit having first and second transistors. The first transistor includes a plurality of trenches extending into a semiconductor substrate and a plurality of source regions, each source region located between a pair of adjacent trenches. A first source terminal is connected to the plurality of source regions. The second transistor includes a central source region between a pair of the trenches and a second source terminal connected to the central source region. The second source terminal is conductively isolated from the first source terminal.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Eung Jung Kim, Thomas Grebs, Sunglyong Kim, Sungho Beck, Wei Fu, Xiaochun Zhao, Arjun Pankaj
  • Publication number: 20250036361
    Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format conversion pipeline including a plurality of parallel format conversion units configured to convert a plurality of input data elements from a first one of a plurality of datatype formats to a second one of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Applicant: Intel Corporation
    Inventors: Supratim Pal, Jiasheng Chen, Kevin Hurd, Jorge E. Parra Osorio, Christopher Spencer, Guei-Yuan Lueh, Pradeep K. Golconda, Fangwen Fu, Wei Xiong, Hongzheng Li, James Valerio, Mukundan Swaminathan, Nicholas Murphy, Shuai Mu, Clifford Gibson, Buqi Cheng