Abstract: An array substrate includes a base substrate, a first conductive layer, a first electrode, an organic planarization layer and an organic active layer. The first conductive layer is provided on a side of the base substrate. The first electrode is provided on a side of the first conductive layer away from the base substrate, an orthographic projection of the first electrode on the base substrate overlapping an orthographic projection of the drain electrode on the base substrate. The organic planarization layer is provided on a side of the first electrode away from the base substrate, first via holes being provided in the organic planarization layer. The organic active layer is provided on a side of the organic planarization layer away from the base substrate, the organic active layer being connected to the source electrode by a first via hole and connected to the drain electrode by a first via hole.

Abstract: The present invention belongs to the technical field of lightning protection of power transmission lines, and in particular, relates to a method for limiting lightning overvoltage of a direct-current power transmission line. By means of using operation date of a line itself, lightning current monitoring data, and parameters of an environment where the line is located, a line dynamic operation function curve and a line lightning-protection performance function curve are both corrected to obtain a more realistic voltage difference, thus achieving reliable protection actions and state sensing of a lightning arrester on the line. An apparatus for limiting a lightning overvoltage of a direct-current power transmission line is further provided in the present invention to cooperate with the implementation of the method.

Abstract: A display substrate includes a base substrate having a display region and a bezel region; in the bezel region, a shift register includes an output transistor, a first electrode of the output transistor is an output end of the shift register; a patch panel is between the shift register and the display region, includes a first sub-patch panel on the same layer as the gate of the output transistor; a common electrode wire is between the shift register and the display region, there is a gap between the common electrode wire and the patch panel; a jumper includes a first sub-jumper and a second sub-jumper, the first sub-jumper is above a layer where the output transistor is, and the second sub-jumper is arranged on a different layer from the first sub-patch panel; the first sub-jumper and the first sub-patch panel overlap each other, the second sub-jumper don't overlap the gap.

Abstract: A free standing film is provide, including: 20 to 100 wt %, based on weight of the free standing film, of an irreversibly crosslinked cellulose ether containing 0.1 to 0.6 wt %, based on weight of the crosslinked cellulose ether, of polyether groups. Unit dose packages including the free standing film are also provided.

Abstract: In one aspect, the invention relates to an immunogenic composition comprising modified O-polysaccharide molecules derived from E. coli lipopolysaccharides and conjugates thereof. Multivalent vaccines may be prepared by combining two or more monovalent immunogenic compositions for different E. coli serotypes. In one embodiment, the modified O-polysaccharide molecules are produced by a recombinant bacterium that includes a wzz gene.

Abstract: An encoding method, a decoding method, and an apparatus are provided. The methods include: A transmit end obtains a first bit sequence, performs LDPC encoding based on the first bit sequence to obtain a second bit sequence, and sends the second bit sequence. The first bit sequence includes K0 information bits, sparsity of the first bit sequence is first sparsity, the second bit sequence includes K1 information bits and N1 parity bits, a value of K1 is determined based on the first sparsity, K1 is less than K0, and K1 is a nonnegative integer. Correspondingly, a receive end obtains the second bit sequence, and then performs LDPC decoding on the second bit sequence based on the first sparsity and a code rate, to obtain the K0 information bits.

Abstract: A display substrate, a method of manufacturing the display substrate, a display panel, and a display device are provided. The display panel includes: an array substrate and an opposite substrate disposed opposite to each other; a liquid crystal layer between the array substrate and the opposite substrate; a first support component on a side of the array substrate facing the liquid crystal layer; and a second support component on a side of the opposite substrate facing the liquid crystal layer. An end portion of a side of the first support component facing away from the array substrate is contacted with an end portion of a side of the second support component facing away from the opposite substrate, and a contact surface has a concave-convex structure.

Abstract: Described are a system, method, and computer program product for dynamic node classification in temporal-based machine learning classification models. The method includes receiving graph data of a discrete time dynamic graph including graph snapshots, and node classifications associated with all nodes in the discrete time dynamic graph. The method includes converting the discrete time dynamic graph to a time-augmented spatio-temporal graph and generating an adjacency matrix based on a temporal walk of the time-augmented spatio-temporal graph. The method includes generating an adaptive information transition matrix based on the adjacency matrix and determining feature vectors based on the nodes and the node attribute matrix of each graph snapshot.

Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

Abstract: This application discloses encoding and decoding methods and a related apparatus, and is applied to the coding field. The method includes: obtaining a to-be-encoded first transport block; obtaining F sub-transport blocks based on the first transport block, where probability distributions of all preprocess blocks included in any sub-transport block belong to a same probability distribution range, and probability distributions of preprocess blocks included in at least two of the F sub-transport blocks belong to different probability distribution ranges; encoding the F sub-transport blocks to obtain a second transport block, where the second transport block includes F encoded sub-transport blocks, and at least two of the F encoded sub-transport blocks correspond to different code rates; and performing transmission based on the second transport block.

Abstract: A layered catalyst structure for purifying an exhaust gas stream includes a catalyst support and a rhodium catalyst layer including an atomic dispersion of rhodium ions and/or rhodium atoms adsorbed on an exterior surface of the catalyst support. The catalyst support includes an alumina substrate, a first ceria layer disposed on and extending substantially continuously over the alumina substrate, and a second colloidal ceria layer formed directly on the first ceria layer over the alumina substrate.

Abstract: The present disclosure relates to the field of artificial intelligence chips, specifically involving a neural network computation method and related devices. The computing device of the present disclosure includes a processor, a communication interface, and other processing devices. The processor and the communication interface are connected to each other through a bus to jointly complete the computations specified by a user. The computing device may also include a storage device, which is connected to the processor and other processing devices for data storage of the computing device and other processing devices. Based on an input data arrangement type and a target data arrangement type, the present disclosure performs data arrangement type conversion only on input of an operator at most, which can reduce unnecessary data arrangement type conversions during the computing process, reduce memory overhead, and improve computing efficiency.

Abstract: In an embodiment an interference cancellation method includes generating, by a first device, a first packet, wherein the first packet comprises a first group of elements, a second group of elements, and user data, the first group of elements being different from the second group of elements and sending, by the first device, the first packet to a second device by using at least one pair of subcarriers, wherein two subcarriers in the at least one pair of subcarriers are symmetrical with respect to a direct current subcarrier, and wherein the first packet is usable by the second device to cancel interference in the user data based on the first group of elements and the second group of elements.

Abstract: Provided is a display module, including a base substrate, a plurality of light-emitting patterns, and a plurality of microlens groups corresponding to the light-emitting patterns. An orthographic projection region of at least one of the light-emitting patterns on the base substrate forms a primary display region. The plurality of microlens groups are disposed on a side, distal from the base substrate, of the plurality of light-emitting patterns. An orthographic projection of the microlens group on the base substrate is within the primary display region formed by the corresponding light-emitting pattern. The microlens group includes at least two microlens structures, and a gap is defined between any adjacent two microlens structures. The light-emitting pattern includes a target region. An orthographic projection of the target region on the base substrate is overlapped with an orthographic projection of the gap on the base substrate. The target region does not emit light.

Abstract: The invention provides a method for constructing a target prediction model in a multicenter small sample scenario and a prediction method. In combination with the idea of transfer learning, a training set of a new node is predicted by directly using knowledge of a trained node, and a prediction error sample is used to reflect a difference between the new node and the trained node. The difference is used as supplementary knowledge. Model knowledge of the new node is quickly acquired, to avoid training of a new node from scratch each time. Finally, parallel integration of incremental subclassifiers is implemented by using a ridge regression method, so that the deployment time and costs are greatly reduced. The generalization of models is ensured through sharing of historical knowledge and a knowledge discarding mechanism, good classification effect can also be achieved for a node with a small sample size.

Abstract: A static voltage stability margin evaluation method and system, and a terminal device are related to the field of integrated energy system operation. The method includes the following steps: establishing a thermal dynamic model of a heating system; establishing a thermoelectric coupling device model; establishing a static voltage stability margin model of an electric power system that considers thermal dynamics of the heating system; and solving the model to obtain a voltage stability margin. In the present invention, a static voltage stability margin that considers thermal dynamics of a heating system can be obtained, and a Pareto boundary of the static voltage stability margin that considers the thermal dynamics can be obtained through a dual-objective nonlinear optimization method, so that an impact of thermoelectric coupling on voltage stability and an impact of thermal inertia of the heating system on a voltage stability margin can be revealed.

Abstract: The present disclosure provides an engineered Hansenula fungus that efficiently expresses CA10 (Coxsackievirus A10) virus-like particles and uses thereof. The engineered fungus includes a recombinant vector carrying the P1 and 3CD genes of the CA10 virus optimized according to preferred codons of Hansenula. The present disclosure also provides a preparation method for CA10 virus-like particles and vaccines prepared therefrom.

Abstract: Embodiments of the present disclosure relate to a gearbox housing. The gearbox housing has a housing body and an annular gear. The housing body comprises an annular support and a lateral portion provided at a side face of the annular support. The lateral portion has a hole formed thereon for an input shaft to pass through. The annular gear is provided inside of the housing body along a radial direction and adapted to couple to the annular support, wherein a plurality of teeth are circumferentially provided at an inner side of the annular gear. A gear wheel with an output shaft is adapted to couple to the plurality of teeth.

Abstract: The present invention describes an electric-thermal-hydrogen multi-energy device planning method for zero energy buildings, including the following specific steps: firstly, constructing operation constraints of electric and thermal devices in the zero energy buildings; secondly, constructing operation constraints of hydrogen devices including the electrolyzer, the fuel cell and the hydrogen storage device; then, in view of constraints on annual zero energy of the buildings, establishing the robust electric-thermal-hydrogen multi-energy device planning model considering source-load uncertainties; and finally, solving the robust electric-thermal-hydrogen multi-energy device planning model of the zero energy buildings by adopting an alternating optimization procedure based column-and-constraint generation algorithm.