Patents by Inventor Wei-Han Chen

Wei-Han Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153564
    Abstract: Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Applicant: Macronix International Co., Ltd.
    Inventors: Wei-Han Chen, Chun-Hsiung Hung
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240139301
    Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 2, 2024
    Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
  • Publication number: 20240128324
    Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
  • Patent number: 11944486
    Abstract: An analysis method and an electronic apparatus for breast image are provided. The method includes the following steps. One or more breast ultrasound images are obtained. The breast ultrasound images are used for forming a three-dimensional (3D) breast model. A volume of interest (VOI) in the breast ultrasound image is obtained by applying a detection model on the 3D breast model. The VOI is compared with a tissue segmentation result. The VOI is determined as a false positive according to a compared result between the VOI and the tissue segmentation result. The compared result includes that the VOI is located at a glandular tissue based on the tissue segmentation result. In response to the VOI being located in the glandular tissue of the tissue segmentation result, the VOI is compared with the lactiferous duct in the 3D breast model.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIHAO MEDICAL INC.
    Inventors: Jen-Feng Hsu, Hong-Hao Chen, Rong-Tai Chen, Hsin-Hung Lai, Wei-Han Teng
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Patent number: 11935757
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20240084148
    Abstract: The present application provides a method of preparing lithium-friendly colloid paint. The method comprises functionalizing a carbon nanotube material to obtain a plurality of carbon nanotubes with functional groups; dispersing the of carbon nanotube material with functional groups in a solution containing nitrogen molecules to from the dispersion liquid to obtain a carbon nanotube precursor; heat-treating the carbon nanotube precursors to obtain a plurality of nitrogen-doped carbon nanotubes; dispersing the plurality of nitrogen-doped carbon nanotubes in an organic solvent, and adding a dispersant obtain a nitrogen-doped carbon nanotube solution precursor; and providing a polymer material colloid and a lithium salt, and uniformly mixing the nitrogen-doped carbon nanotube solution precursor, the lithium salt and the polymer material colloid.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 14, 2024
    Inventors: WEI-CHAO CHEN, PIN-HAN WANG, HONG-ZHENG LAI, TSENG-LUNG CHANG
  • Publication number: 20240078170
    Abstract: A setting method of in-memory computing simulator includes: performing a plurality of test combinations by an in-memory computing device and recording a plurality of first estimation indices corresponding to the plurality of test combinations respectively, wherein each of the plurality of test combinations includes one of a plurality of neural network models and one of a plurality of datasets, executing a simulator according to the plurality of test combinations by a processing device and recording a plurality of second estimation indices corresponding to the plurality of test combinations respectively, wherein the simulator has a plurality of adjustable settings; calculating a correlation sum according to the plurality of first estimation indices and the plurality of second estimation indices by the processing device, and performing an optimal algorithm to search an optimal parameter in the setting space constructed by the plurality of settings so that the correlation sum is maximal.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 7, 2024
    Inventors: Ke-Han Li, Chih-Fan Hsu, Yu-Sheng Lin, Wei-Chao CHEN
  • Patent number: 11923205
    Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
  • Publication number: 20240069619
    Abstract: A method, system, and article provide image processing with power reduction while using universal serial bus cameras.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Intel Corporation
    Inventors: Ko Han Wu, Thiam Wah Loh, Kenneth K. Lau, Wen-Kuang Yu, Ming-Jiun Chang, Andy Yeh, Wei Chih Chen
  • Patent number: 11916155
    Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 27, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
  • Publication number: 20230387271
    Abstract: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ya-Yi Tsai, Yi-Chun Chen, Wei-Han Chen, Wei-Ting Guo, Shu-Yuan Ku
  • Patent number: 11791403
    Abstract: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Yi Tsai, Yi-Chun Chen, Wei-Han Chen, Wei-Ting Guo, Shu-Yuan Ku
  • Publication number: 20230234055
    Abstract: An optoelectronic tweezer device includes a transparent substrate, a semiconductor layer, a first electrode and a dielectric layer. The semiconductor layer is located above the transparent substrate and includes a first doping region, a second doping region and a transition region, wherein the transition region is located between the first doping region and the second doping region. The first electrode is located on the first doping region and is electrically connected to the first doping region. The dielectric layer is located above the semiconductor layer and has a first through hole overlapping the first electrode.
    Type: Application
    Filed: May 23, 2022
    Publication date: July 27, 2023
    Applicant: Au Optronics Corporation
    Inventors: Shih-Hua Hsu, Wei-Han Chen, Ching-Wen Chen, Ying-Hui Lai
  • Publication number: 20230061323
    Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.
    Type: Application
    Filed: August 28, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Yi Tsai, Shih-Yao Lin, Chi-Hsiang Chang, Wei-Han Chen, Shu-Yuan Ku
  • Publication number: 20230067752
    Abstract: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.
    Type: Application
    Filed: August 28, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Yi Tsai, Yi-Chun Chen, Wei-Han Chen, Wei-Ting Guo, Shu-Yuan Ku
  • Patent number: 11586948
    Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: February 21, 2023
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Wen-Liang Chen, Lung-Chieh Chen, Szu-Chia Chen, Wei-Han Chen, Chun-Yu Chu, Yu-Chi Shih, Yu-Ci Chang, Tzu-I Hsieh, Yen-Ling Chen, Li-Chi Peng, Meng-Zhan Lee, Jui-Yu Ho, Chi-Yao Ku, Nian-Ruei Deng, Yuan-Yao Chan, Erick Wang, Tai-Hsiang Yen, Shao-Yu Chiu, Jiun-Yi Lin, Yun-Wei Lin, Fung Ling Ng, Yi-Bing Lin, Chin-Cheng Wang
  • Patent number: 11364413
    Abstract: A reaction force detection system for treadmills and detection method thereof is disclosed, wherein the system detects the current data generated by a user running on a treadmill comprising a running belt, a motor and an electronic circuit device by means of a current sensor, and then determines a current peak based on the current data, such that a ground reaction force peak can be determined according to the acquired current peak. Therefore, the present invention allows to determine the ground reaction force of the human body during running through the changes of the motor current signals inside the treadmill, such that these parameters can be further presented, analyzed, and stored in order to provide more scientific feedbacks for running trainings.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: June 21, 2022
    Assignee: NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tzyy-Yuang Shiang, Wen-Wen Yang, Wei-Han Chen, En-Tzu Wang
  • Publication number: 20210004694
    Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.
    Type: Application
    Filed: October 20, 2019
    Publication date: January 7, 2021
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Wen-Liang Chen, Lung-Chieh Chen, Szu-Chia Chen, Wei-Han Chen, Chun-Yu Chu, Yu-Chi Shih, Yu-Ci Chang, Tzu-I Hsieh, Yen-Ling Chen, Li-Chi Peng, Meng-Zhan Lee, Jui-Yu Ho, Chi-Yao Ku, Nian-Ruei Deng, Yuan-Yao Chan, Erick Wang, Tai-Hsiang Yen, Shao-Yu Chiu, Jiun-Yi Lin, Yun-Wei Lin, Fung Ling Ng, Yi-Bing Lin, Chin-Cheng Wang