Abstract: A memory device may be a 3D NAND flash memory circuit, and provides a high-capacity storage medium with favorable performance. The memory device includes a plurality of page buffers and a plurality of first switches. The page buffers are coupled in series. The first switches respectively correspond to the page buffers, wherein each of the first switches is coupled to a sensing node of corresponding page buffer. Each of the first switches receives a reference voltage and provides a source current to the sensing node of corresponding page buffer after a data sensing period.

Abstract: A memory device and a detection method for detecting a defeated status of a memory cell are provided. The memory device is, for example a three dimensional NAND flash memory circuit, and provides a storage media with high-performance and high-capacity. The detection method includes: searching status data stored in a page buffer, finding set status memory cells, and acquiring set status data; storing status data in a storage device; setting one of latches in the page buffer as a selected latch after a first half of the levels of the programming operation have been completed; storing each setting data in the selected latch; and check each set status memory cell according to the each set status data to determine whether the set status memory cell is maintained in the set status.

Abstract: An optoelectronic tweezer device includes a transparent substrate, a semiconductor layer, a first electrode and a dielectric layer. The semiconductor layer is located above the transparent substrate and includes a first doping region, a second doping region and a transition region, wherein the transition region is located between the first doping region and the second doping region. The first electrode is located on the first doping region and is electrically connected to the first doping region. The dielectric layer is located above the semiconductor layer and has a first through hole overlapping the first electrode.

Abstract: An optoelectronic tweezer device includes a transparent substrate, a semiconductor layer, a first electrode and a dielectric layer. The semiconductor layer is located above the transparent substrate and includes a first doping region, a second doping region and a transition region, wherein the transition region is located between the first doping region and the second doping region. The first electrode is located on the first doping region and is electrically connected to the first doping region. The dielectric layer is located above the semiconductor layer and has a first through hole overlapping the first electrode.

Abstract: Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. Multiple fins are formed extending from the substrate, the fins including a first group of active fins in an active region and an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions, the inactive fin separated from its closest active fin by a second trench region, and the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

Abstract: A semiconductor device includes a semiconductor substrate; an isolation region disposed on the semiconductor substrate; a plurality of dummy fins disposed over the isolation region and partially extending into the isolation region; and a dielectric material disposed between the plurality of dummy fins, and partially extending through the isolation region and partially into the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.

Abstract: Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.

Abstract: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.

Abstract: An optoelectronic tweezer device includes a transparent substrate, a semiconductor layer, a first electrode and a dielectric layer. The semiconductor layer is located above the transparent substrate and includes a first doping region, a second doping region and a transition region, wherein the transition region is located between the first doping region and the second doping region. The first electrode is located on the first doping region and is electrically connected to the first doping region. The dielectric layer is located above the semiconductor layer and has a first through hole overlapping the first electrode.

Abstract: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.

Abstract: A reaction force detection system for treadmills and detection method thereof is disclosed, wherein the system detects the current data generated by a user running on a treadmill comprising a running belt, a motor and an electronic circuit device by means of a current sensor, and then determines a current peak based on the current data, such that a ground reaction force peak can be determined according to the acquired current peak. Therefore, the present invention allows to determine the ground reaction force of the human body during running through the changes of the motor current signals inside the treadmill, such that these parameters can be further presented, analyzed, and stored in order to provide more scientific feedbacks for running trainings.

Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.

Abstract: A reaction force detection system for treadmills and detection method thereof is disclosed, wherein the system detects the current data generated by a user running on a treadmill comprising a running belt, a motor and an electronic circuit device by means of a current sensor, and then determines a current peak based on the current data, such that a ground reaction force peak can be determined according to the acquired current peak. Therefore, the present invention allows to determine the ground reaction force of the human body during running through the changes of the motor current signals inside the treadmill, such that these parameters can be further presented, analyzed, and stored in order to provide more scientific feedbacks for running trainings.

Abstract: A pixel structure including a substrate, a power wire, a planarization layer, a drive circuit and a conductive structure is provided. The substrate has a layout area and a light-transmitting area located outside the layout area. The power wire is disposed on the layout area of the substrate. The power wire includes a shielding layer. The planarization layer is disposed on the substrate and covers the power wire. The drive circuit is disposed on the planarization layer and corresponds to the layout area. The drive circuit includes a first active device. The shielding layer overlaps with the first active device. The conductive structure is disposed in the planarization layer and distributed corresponding to the layout area. The power wire is electrically connected with the drive circuit through the conductive structure. A display panel is also provided.