Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: Described herein is a server that includes a server chassis having a front window for providing access to an interior receptacle of the server chassis. A docking station is located in the interior receptacle. The server also includes a PCIe module coupled to the docking station by a coupling element. The PCIe module protrudes externally from the interior receptacle through the front window in the docked position. The PCIe module can be moved to a plurality of undocked positions while remaining coupled to the docking station.

Abstract: Described herein is a server that includes a server chassis having a front window for providing access to an interior receptacle of the server chassis. A docking station is located in the interior receptacle. The server also includes a PCIe module coupled to the docking station by a coupling element. The PCIe module protrudes externally from the interior receptacle through the front window in the docked position. The PCIe module can be moved to a plurality of undocked positions while remaining coupled to the docking station.

Abstract: A synthetic jet includes a casing, a vibrating membrane and a guiding channel. The casing has a chamber. The casing has an inlet and an outlet opposite to each other. The inlet and the outlet communicate with the chamber. The chamber is configured to accommodate gas. The outlet corresponds to a heat source. The vibrating membrane isolates and divides the chamber into a first subsidiary chamber and a second subsidiary chamber. The inlet communicates with the first subsidiary chamber. The second subsidiary chamber has a second subsidiary chamber opening communicating with the outlet. The guiding channel communicates with the first subsidiary chamber and the outlet. When being driven, the vibrating membrane reciprocally deforms towards the first subsidiary chamber and the second subsidiary chamber.

Abstract: A fin assembly includes multiple first fins, multiple second fins and a heat pipe. An interval is formed between every two of the first fins which are neighboring to each other. The first fins and the second fins are alternately arranged with each other. The heat pipe penetrates through the plurality of first fins and the plurality of second fins. A partial volume of each second fin is disposed inside each interval, respectively.

Abstract: A chip-to-chip communications circuit which is particularly well-suited for short range wired RF communication from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. During a phase calibration cycle, a phase adjustment controller in the transmitter interoperates with a phase adjustment controller in the receiver, to adjust a phase locked-loop (PLL) circuit to correct for the phase delay arising in response to signal propagation between transmitter and receiver.