Abstract: Disclosed are systems, methods, and other implementations, including a method for detecting machine-generated content that includes receiving written source input at a machine learning system configured to transform written content into resultant transformed content, and generating by the machine learning system one or more rewritten versions of the written source input, with the one or more rewritten versions being semantically similar to the written source input. The method further includes deriving one or more rewriting change measurements, for the one or more rewritten versions, representing extent of differences between the one or more rewritten versions and the written source input, and determining likelihood that the written source input was machine generated based at least on the derived one or more rewriting change measurements.

Abstract: A vapor chamber may include a first plate, evaporator wick structure, second plate, condenser wick structure, and plurality of heat pipes. The first plate includes a first inner surface, a first outer surface, and plurality of chamber walls extending from the first inner surface and having second and third chamber walls. The evaporator wick structure is disposed on the first inner surface. The condenser wick structure is disposed on a second inner surface of the second plate. The second plate is coupled to the plurality of chamber walls and plurality of heat pipes. At least one set of the heat pips is disposed through one chamber wall and another set of the heat pipes is disposed through the opposite chamber wall. Each of the heat pipes includes an inner chamber surface and pipe wick structure. The pipe wick structure is disposed on the inner chamber surface and coupled to the evaporator wick structure.

Abstract: A semiconductor device includes a substrate having a first planar region, a second planar region adjacent to the first planar region, a non-planar region between the first planar region and the second planar region, a first base on the first planar region, a second base on the second planar region, and a plurality of bumps on the non-planar region. Preferably, the bumps have different heights, top surfaces of the first base and the second base are coplanar, the top surface of the bumps is lower than the top surface of the first base, and the height of the bumps closer to the first planar region is greater than the height of the bumps closer to the non-planar region.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Abstract: The present disclosure describes a semiconductor device having a source/drain (S/D) structure with a void. The semiconductor device includes a stack of semiconductor layers on a substrate, a gate structure surrounding the stack of semiconductor layers, and a S/D structure on the substrate and in contact with the stack of semiconductor layers. The S/D structure includes a void below a top surface of the S/D structure.

Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.

Abstract: Retention time drift caused by fluctuations in physical factors such as temperature ramping rate and carrier gas flow rate is ubiquitous in chromatographic measurements. Proper peak identification and alignment across different chromatograms is critical prior to any subsequent analysis. This work introduces a peak identification method called retention time trajectory (RTT) matching, which uses chromatographic retention times as the only input and identifies peaks associated with any subset of a predefined set of target compounds. RTT matching is also capable of reporting interferents. An RTT is a 2-dimensional (2D) curve formed uniquely by the retention times of the chromatographic peaks. The RTTs obtained from the chromatogram of a test sample and of pre-characterized library are matched and statistically compared. The best matched pair implies identification. Unlike most existing peak alignment methods, no mathematical warping or transformations are involved.

Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

Abstract: Embodiments of this application provide a transmission line, a feed network, and an antenna apparatus. The transmission line is used for a radio frequency device. The transmission line includes a reflector, an insulation support, and a transmission structure. The transmission structure includes at least two side walls. The transmission structure is disposed on a surface of the insulation support, an included angle between two adjacent side walls of the transmission structure is greater than zero, and different side walls of the transmission structure are located on different surfaces of the insulation support. At least one surface of the transmission structure is disposed opposite to a part of a structure of the reflector, and a gap exists between the at least one surface of the transmission structure and the reflector. The transmission line has a small signal loss and occupies a small space.

Abstract: Disclosed is a method for short-term traffic risk prediction of road sections by using roadside observation data.

Abstract: The present disclosure is directed to a structure of a gate-all-around field effect transistors (GAAFET) and a method of forming the structure. The structure includes a diffusion barrier structure in an S/D epitaxial structure of the GAAFET. The diffusion barrier structure is in contact with an NS layer of the GAAFET and extends over side surfaces of inner spacer structures adjacent to the NS layer. The diffusion barrier structure separates a high doping region of the S/D epitaxial structure from the NS layer and regions of the inner spacer structures close to the NS layer. The diffusion barrier structure prevents (or mitigates) dopants in the high doping region from diffusing into the NS layer and the inner spacer structures, preserving the integrity of the NS layer as a semiconducting channel of the GAAFET and avoiding a current crowding effect.

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

Abstract: An electronic device and a method for determining the intensity of a low-frequency current are provided. The method includes: individually applying a corresponding first current to a body part of a user in N consecutive time intervals, wherein the time intervals include an i-th time interval to an (i+N)-th time interval; obtaining electromyography values of the body part in each time interval; determining a second current corresponding to an (i+N+1)-th time interval based on the first current corresponding to each time interval, the body part, personal information of the user, and the electromyography values of each time interval; and applying a second current to the body part of the user in the (i+N+1)-th time interval.

Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

Abstract: Disclosed are computer-implemented or computer-aided method for diagnosing or predicting the risk of obstructive sleep apnea in a subject. The methods comprise determining whether the subject has obstructive sleep apnea based on at least one quantitative ultrasound parameter and/or at least one morphometric parameter.

Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

Abstract: An electronic device package and a method for manufacturing the electronic device are provided. The electronic device includes a charging element, a housing covering the charging element and a sensing element electrically connected to the housing. The sensing element is configured to detect an external device and to drive the charging element.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

Abstract: A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer. The MTJ is over the first dielectric layer. The oxide layer is over the first dielectric layer. The cap layer is over the first dielectric layer. The cap layer is in contact with a sidewall of the MTJ and a sidewall of the oxide layer. The second dielectric layer is over the cap layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate, a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect conductive structure arranged within the second interconnect dielectric layer. The interconnect conductive structure includes an outer portion that includes a first conductive material. Further, the interconnect conductive structure includes a central portion having outermost sidewalls surrounding by the outer portion of the interconnect conductive structure. The central portion includes a second conductive material different than the first conductive material.